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公开(公告)号:DE19958151B4
公开(公告)日:2006-05-04
申请号:DE19958151
申请日:1999-12-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor: NELLE PETER , FISCHER HERMANN , WERNER WOLFGANG , SCHAEFER HERBERT
IPC: H01L29/78 , H01L21/336 , H01L29/06
Abstract: Lateral high voltage semiconductor element comprises a semiconductor substrate (1) of first conductivity with a semiconductor layer (2) of second conductivity having an active zone (3). Semiconductor regions (11, 12) of first and second conductivity are provided on the semiconductor layer by selective multiple epitaxy. An Independent claim is also included for a process for the production of a lateral high voltage semiconductor element, comprising back-etching an insulating layer provided on the edges of the semiconductor regions (11, 12) after selective multiple epitaxy and then carrying out further selective epitaxy to form a connecting layer. Preferred Features: The semiconductor regions have a thickness of 1-100 nm, especially 50 nm.
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公开(公告)号:DE10009347A1
公开(公告)日:2001-09-13
申请号:DE10009347
申请日:2000-02-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor: FISCHER HERMANN , NANCE PAUL , KANERT WERNER
IPC: H01L21/331 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/739 , H01L29/749 , H01L29/78 , H01L21/332 , H01L29/74
Abstract: The semiconductor device includes a substrate (5,6,10) with an (n-) type front region and a back region (5) forming a first main connection. An n type well (40') is formed in a first region (10). A p type well (70) is formed in the first region. The second well forms a p type channel region (K) in a portion of the first well. A (n+) type third well is formed in the first region. The third well forms a second main connection in a common portion of the first and second well. A third main connection is provided over the channel region (K).
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公开(公告)号:DE10239310A1
公开(公告)日:2004-03-25
申请号:DE10239310
申请日:2002-08-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: FISCHER HERMANN , WERNER WOLFGANG , MAYER THORSTEN , KANERT WERNER , FUGGER JOSEF
IPC: H01L29/417 , H01L29/78 , H01L21/28 , H01L21/336
Abstract: Production of conducting connection between first trenched layer (2) of first conductivity arranged at distance from front side (101) of semiconductor body (100) and second layer (4) of second conductivity comprises forming recess from front side to first layer, and doping via recess into boundary region between first and second layer to produce strongly doped connecting zone (3). Production of an electrically conducting connection between a first trenched layer (2) of first conductivity arranged at a distance from a front side (101) of a semiconductor body (100) and a second layer (4) of a second conductivity comprises forming a recess (6) extending from the front side up to the first layer, and introducing doping atoms of first and second conductivity via the recess into a boundary region between the first layer and the second layer to produce a connecting zone (3) in the boundary region which is more strongly doped than the first layer forming a tunnel diode with the second layer.
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公开(公告)号:DE10009347C2
公开(公告)日:2003-11-13
申请号:DE10009347
申请日:2000-02-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor: FISCHER HERMANN , NANCE PAUL , KANERT WERNER
IPC: H01L21/331 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/739 , H01L29/749 , H01L29/78 , H01L21/332 , H01L29/74
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公开(公告)号:DE102004058131A1
公开(公告)日:2006-06-08
申请号:DE102004058131
申请日:2004-12-02
Applicant: INFINEON TECHNOLOGIES AG
Inventor: KLEHN BERND , FISCHER HERMANN , BRASS ECKHARD , SCHUMANN THOMAS , KLEIN RALF
IPC: G11C11/4091 , G11C11/407
Abstract: The method involves closing a control unit (MUX) to connect a sense amplifier (SAM) with a bit line (BL), and activating a word line (WL) to activate a memory cell (M) for selection. The sense amplifier is activated to evaluate information of the bit line, and the control unit is opened to disconnect the bit line by the sense amplifier. The selected information is delivered on a data bus (DAT). An independent claim is also included for a dynamic circuit memory with a selection circuit.
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公开(公告)号:DE10239310B4
公开(公告)日:2005-11-03
申请号:DE10239310
申请日:2002-08-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: FISCHER HERMANN , WERNER WOLFGANG , MAYER THORSTEN , KANERT WERNER , FUGGER JOSEF
IPC: H01L29/417 , H01L29/78 , H01L21/28 , H01L21/336
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公开(公告)号:DE19958151A1
公开(公告)日:2001-06-13
申请号:DE19958151
申请日:1999-12-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor: NELLE PETER , FISCHER HERMANN , WERNER WOLFGANG , SCHAEFER HERBERT
IPC: H01L21/336 , H01L29/06 , H01L29/78
Abstract: Lateral high voltage semiconductor element comprises a semiconductor substrate (1) of first conductivity with a semiconductor layer (2) of second conductivity having an active zone (3). Semiconductor regions (11, 12) of first and second conductivity are provided on the semiconductor layer by selective multiple epitaxy. An Independent claim is also included for a process for the production of a lateral high voltage semiconductor element, comprising back-etching an insulating layer provided on the edges of the semiconductor regions (11, 12) after selective multiple epitaxy and then carrying out further selective epitaxy to form a connecting layer. Preferred Features: The semiconductor regions have a thickness of 1-100 nm, especially 50 nm.
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公开(公告)号:DE19954600C1
公开(公告)日:2000-11-16
申请号:DE19954600
申请日:1999-11-12
Applicant: INFINEON TECHNOLOGIES AG
Inventor: FISCHER HERMANN , PFIRSCH FRANK , KANERT WERNER
IPC: H01L27/06 , H01L23/58 , F02N11/08 , F02P3/04 , H01L27/08 , H01L29/06 , H01L29/739 , H01L29/866
Abstract: The IC has a peripheral edge with aluminium or polysilicon rings, a transition from the edge to the Zener diodes and an edge termination in which the Zener diodes are integrated, whereby the Zener diodes have voltage tappings that are not arranged at equal intervals. The distance of the individual rings from the Zener diodes is larger. Aluminium field plates can be arranged over polysilicon rings (SR1-SR5) above an insulating layer and connected to the potential of the rings via contact holes.
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