公开(公告)号：JP2007123893A

公开(公告)日：2007-05-17

申请号：JP2006290462

申请日：2006-10-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK A ,  CHENG KANGGUO

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10841 ,  G11C11/403 ,  G11C11/405 ,  H01L27/0207 ,  H01L27/10864 ,  H01L27/10894 ,  H01L29/045

Abstract: PROBLEM TO BE SOLVED: To provide improved gain and cell and a method for manufacturing and using the same. SOLUTION: In a first embodiment, the memory cell of a substrate containing (1) a PFET having almost planar orientation to the surface of the substrate and (2) an NFET coupled to an almost planar PFET is provided. The orientation of the NFET inside the substrate is almost vertical to that of the PFET. The invention includes many other embodiments. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供改进的增益和电池及其制造和使用方法。 解决方案：在第一实施例中，提供了一种衬底的存储单元，其包含（1）具有与衬底表面几乎平面取向的PFET和（2）耦合到几乎平面的PFET的NFET。 衬底内部NFET的取向几乎与PFET垂直。 本发明包括许多其它实施例。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004015053A

公开(公告)日：2004-01-15

申请号：JP2003151411

申请日：2003-05-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK A ,  HO HERBERT L

IPC: H01L21/334 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10867 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1203 ,  H01L29/66181

Abstract: PROBLEM TO BE SOLVED: To increase the degree of vertical separation between a passing wordline and a strap.
SOLUTION: If the thickness of an insulation layer is decreased in an SOI integrated circuit including a trench capacitor DRAM array, crosstalk is caused between a trench capacitor and the passing wordline 214 which passes over the trench capacitor. The buried strap on a capacitor center electrode 105 is enabled to come into contact with the backside of an SOI layer 60 by increasing the depth of a recess at the upper part of the trench and laterally undercutting the insulating layer, thereby increasing the degree of vertical separation between the passing wordline 214 and the strap.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002305287A

公开(公告)日：2002-10-18

申请号：JP2002016927

申请日：2002-01-25

Applicant: IBM

Inventor： MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal-oxide film semiconductor integrated circuit which contains a notched gate in a support device region, and to provide a method of forming the integrated circuit. SOLUTION: A gate stack 16 is formed on a substrate, a patterned mask 24 is formed on the gate stack, the stack gate is etched by using the mask, and rather than the entire part but a part of a gate conductor is removed. A gap-filling film 28 is formed on the whole face, and the gap-filling film is removed in such a way that the gap filling film is left between masked gate stacks in an array device region. A spacer is formed on the exposed sidewall of the masked gate stack, and the exposed gate conductor inside the array device region and inside the support device region is removed. An undercut is formed in the lower exposed part of the remaining gate conductor. The remaining gap filling film is removed from the masked protective gate stack inside the array device region.

公开(公告)号：JP2002222873A

公开(公告)日：2002-08-09

申请号：JP2001388866

申请日：2001-12-21

Applicant: IBM

Inventor： RAMACHANDORA DEIVAKARUNI ,  LEE HEON ,  MANDELMAN JACK A ,  RADENS CARL J ,  SIM JAI-HOON

IPC: H01L21/8242 ,  H01L21/336 ,  H01L27/108 ,  H01L29/772

Abstract: PROBLEM TO BE SOLVED: To provide an improved method of forming a vertical MOSFET structure. SOLUTION: A method of forming a semiconductor memory cell array structure comprises a process of providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer 22 planarized up to the top surface of a trench top oxide 24 on a silicon substrate, a process of forming a recess 39 in the gate conductor layer below the top surface of the silicon substrate, a process of forming doping pockets 46 in an array P well 32 by implanting N-type dopant species through the recess at an angle, a process of forming spacers 44 on the side wall of the recess by depositing an oxide layer in the recess and then etching the oxide layer, and a process of depositing a gate conductor material in the recess and then planarizing the gate conductor material up to the top surface of the trench top oxide.

公开(公告)号：JP2001345383A

公开(公告)日：2001-12-14

申请号：JP2001160548

申请日：2001-05-29

Applicant: IBM

Inventor： CLAUDEL L BARTIN ,  RAMACHANDORA DEIVAKARUNI ,  HOUGHTON RUSSELL J ,  MANDELMAN JACK A ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide an anti-fuse structure which can program at a low voltage and current, uses only in an extremely small chip base, and can be formed in a gap between parts which are disposed at intervals of a least lithographic feature size. SOLUTION: An anti-fuse structure is formed on an SOI substrate in combination with a capacitor-like structure which reaches support layer or in the support layer by etching a contact which penetrates an insulator and reaches the support semiconductor layer. This anti-fuse can be programmed by selecting a position forming a conductor or damaging a dielectric of the capacitor-like structure. It is possible to restrict the damages to a desirable position by use of an insulation collar enclosing the conductor or a part of the capacitor-like structure. Thermal influences due to a programming current are isolated into the interior of a bulk silicon layer, whereby a programming during a normal operation of a device is enabled.

公开(公告)号：JP2001007223A

公开(公告)日：2001-01-12

申请号：JP2000160941

申请日：2000-05-30

Applicant: IBM

Inventor： JEFFREY P GANBINO ,  LEWIS L SUU ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a dual work function gate conductor having a self-aligned insulating cap, and a method for forming the dual work function gate conductor. SOLUTION: Two diffusion regions 36 are formed on a substrate 20, and gate stacks 33 and 34 are formed on the substrate 20 between these regions 36. The stacks 33 and 34 have a gate insulating layer 24, and polysilicon layers 26 and 26a on the layer 24, respectively. The layers 26 and 26a are n-type doped and remain intrinsic. A barrier layer 28 is formed on each of the layers 26 and 26a. A dopant source 30 is formed on the layer 28 for both stacks 33 and 34. The layer 28 has a p-type dopant. The stacks 33 and 34 are covered with an insulating cap 32 so that diffusion contacts can be formed on the gates in a borderless manner. When to start activating the source 30 for doping the layers 26 and 26a can be postponed until the desired timing.

公开(公告)号：JP2000183302A

公开(公告)日：2000-06-30

申请号：JP35805299

申请日：1999-12-16

Applicant: IBM ,  SIEMENS AG

Inventor： SUSAN E SHARUU ,  TSUE CHIAN CHEN ,  JONATHAN E FALTERMAIER ,  GRUENING ULRIKE ,  RAJARAAO JANMII ,  MANDELMAN JACK A ,  PARKS CHRISTOPHER C ,  PAUL C PARIIZU ,  PAUL A RONSUHAIMU ,  YUN YUU WAN

IPC: B82B1/00 ,  H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain a trench capacitor structure in which mutual influence can be reduced between the regions whose crystallization levels are different. SOLUTION: In a trench capacitor 40, a substrate 60 is provided with a trench 44, an embedded plate electrode 42, a node dielectric 46, an oxide collars 48, trench electrode materials 50, and a conductive type strap 56. A quantum conductive layer which is a silicon nitride thin film is arranged on a boundary face 58 between the conductive strap 56 and the substrate 60 and a boundary face 62 between the trench electrode 50 and the conductive strap 56. The transmission of the recrystallizing force of the trench electrode 50 and the strap 56 to the strap 56 or the substrate 60 can be reduced by this quantum conductive layer. Thus, the reliability of the device can be improved.

公开(公告)号：JP2000091525A

公开(公告)日：2000-03-31

申请号：JP25944099

申请日：1999-09-13

Applicant: IBM

Inventor： JAMMY RAJARAO ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor memory structure, especially a deep trench semiconductor memory device for which a temperature sensitive high dielectric constant material is taken inside the storage node of a capacitor. SOLUTION: In this manufacturing method, after shallow trench separation at high temperature and processing a gate conductor, a deep trench storage capacitor is manufactured. With the manufacturing method, a temperature sensitive high dielectric constant material can be taken into a capacitor structure without causing decomposition of the material. Furthermore, the manufacturing method limits the spread of a buried strap outward diffused part 44, and thus the electric characteristics of an array MOSFET are improved.

公开(公告)号：JPH10256394A

公开(公告)日：1998-09-25

申请号：JP3865098

申请日：1998-02-20

Applicant: IBM

Inventor： DONALD C WHEELER ,  LEWIS L SUU ,  MANDELMAN JACK A ,  REBECCA D MI

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a new structure, especially a CMOS structure, decreasing off-state current of a device. SOLUTION: A MOS transistor 70 contains two trench isolation regions 78 adjoining an active region 79. The trench isolation regions 78 is disposed on the opposite sides of the active region 79 so that side walls 80 of each trench acts as an interface for the active region 79, and at least one of the side walls 80 has inclination of 90-150 deg.. The trench isolation regions 78, a source injection region and a drain injection region 78 surround all sides of the active region 79.

公开(公告)号：JPH1074907A

公开(公告)日：1998-03-17

申请号：JP16576497

申请日：1997-06-23

Applicant: SIEMENS AG ,  IBM

Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  POSCHENRIEDER BERNHARD ,  SHORT ALVIN P ,  SRINIVASAN RADHIKA ,  STENGL REINHARD J ,  HO HERBERT L

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: A device layout has a device structure including a first device and a second device formed thereon, and an active region of the second region is located inside the upper surface so as to facilitate a three-dimensional device layout. SOLUTION: For example, a highly doped N polylayer is next formed on the surface. This polylayer is planarized up to an upper surface of a gate 895 to form a bit-line contact area 110. An MO dielectric layer is layed to expose the contact area 110. A metal layer 150 is next deposited so as to fill an contact opening 120. This metal layer 150 is etched for forming a bit-line conductor. The capacity of spatially positioning a device on a trench allows a more effective three-dimensional layout. As a result, the density of a device for a prescribed area can be increased.