公开(公告)号：FR2978602A1

公开(公告)日：2013-02-01

申请号：FR1156990

申请日：2011-07-29

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2 ,  IBM

Inventor： DUTARTRE DIDIER ,  BREIL NICOLAS ,  CAMPIDELLI YVES ,  GOURHANT OLIVIER

IPC: H01L21/205 ,  H01L21/822

Abstract: L'invention concerne un procédé de dépôt d'une couche d'oxyde de silicium (32) sur un substrat comprenant une région de silicium et une région de silicium-germanium, comprenant les étapes suivantes : former une couche très mince de silicium (30) d'une épaisseur de 0,1 à 1 nm au-dessus du silicium-germanium ; et déposer une couche d'oxyde de silicium (32) sur le substrat.

公开(公告)号：FR2952225B1

公开(公告)日：2012-03-23

申请号：FR0957769

申请日：2009-11-03

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2

Inventor： DUTARTRE DIDIER ,  CAMPIDELLI YVES ,  LOUBET NICOLAS

IPC: H01L21/335 ,  H01L21/8238 ,  H01L29/78

公开(公告)号：FR2900275A1

公开(公告)日：2007-10-26

申请号：FR0603454

申请日：2006-04-19

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  BROSSARD FLORENCE ,  VANDELLE BENOIT

IPC: H01L21/20 ,  C30B25/04

Abstract: Une portion monocristalline (1) à base de silicium est réalisée sur un substrat (100), sélectivement dans une zone (101) où un matériau monocristallin est initialement découvert. La portion est réalisée en dehors de zones où la surface (S) du substrat est en matériau isolant (102). La portion monocristalline est formée à partir d'un mélange gazeux comprenant un précurseur de silicium du type hydrure non-chloré, du chlorure d'hydrogène et un gaz porteur. Le procédé permet de réduire une température de chauffage du substrat nécessaire pour former la portion monocristalline par croissance épitaxiale sélective.

公开(公告)号：FR2779572B1

公开(公告)日：2003-10-17

申请号：FR9807059

申请日：1998-06-05

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L29/73 ,  H01L29/732

Abstract: A vertical bipolar transistor production process comprises epitaxy of a single crystal silicon emitter region in direct contact with the upper layer of a silicon germanium heterojunction base. Production of a vertical bipolar transistor comprises (a) forming an intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate (1); (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well (60); (c) forming an silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a multilayer (8) including a silicon germanium layer; and (e) forming an in-situ doped emitter by epitaxy on a window of the surface of the multilayer located above the intrinsic collector to obtain, above the window, a single crystal silicon emitter region in direct contact with the upper layer of the multilayer (8). An Independent claim is also included for a vertical bipolar transistor produced by the above process.

公开(公告)号：FR2807208B1

公开(公告)日：2003-09-05

申请号：FR0003983

申请日：2000-03-29

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  FOURNEL RICHARD ,  DUTARTRE DIDIER ,  RIBOT PASCAL ,  PAOLI MARYSE

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L21/8239

Abstract: A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly applicable to EPROM, EEPROM, Flash and single-electron memories using CMOS technology.

公开(公告)号：FR2822292B1

公开(公告)日：2003-07-18

申请号：FR0103469

申请日：2001-03-14

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  BAUDRY HELENE ,  DUTARTRE DIDIER

IPC: H01L21/331 ,  H01L29/737

公开(公告)号：FR2823032A1

公开(公告)日：2002-10-04

申请号：FR0104510

申请日：2001-04-03

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  DUTARTRE DIDIER ,  RIBOT PASCAL

IPC: H03H3/00 ,  H03H9/24 ,  H03H9/00

Abstract: The electromechanical resonator has an active zone (1) made of strongly doped monocrystalline silicon making a first electrode. There are isolating zones (2) carrying the monocrystalline silicon and leaving a central spaced zone.

公开(公告)号：FR2802705B1

公开(公告)日：2002-08-09

申请号：FR9915902

申请日：1999-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  DUTARTRE DIDIER

IPC: H01L21/20 ,  H01L21/762 ,  H01L29/06 ,  H01L21/3213 ,  B82B1/00 ,  B82B3/00

Abstract: The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.