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    CAPTEUR ECLAIRE PAR LA FACE ARRIERE A ISOLEMENT PAR JONCTION
    63.
    发明专利
    CAPTEUR ECLAIRE PAR LA FACE ARRIERE A ISOLEMENT PAR JONCTION 未知

    公开(公告)号：FR2974240A1

    公开(公告)日：2012-10-19

    申请号：FR1153183

    申请日：2011-04-12

    Applicant: ST MICROELECTRONICS CROLLES 2 ,  ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  PRIMA JENS ,  ROY FRANCOIS

    IPC: H01L27/146

    Abstract: L'invention concerne un procédé de réalisation d'un capteur d'images (31) à éclairement par la face arrière comportant les étapes suivantes : a) former, depuis la face avant, des régions (35) de silicium polycristallin dopé, de type de conductivité opposé à celui du substrat (33), s'étendant en profondeur orthogonalement à ladite face avant ; b) amincir le substrat par sa face arrière jusqu'à atteindre les régions (35) de silicium polycristallin ; c) déposer, sur la face arrière du substrat aminci, une couche de silicium amorphe (41) dopé, de type de conductivité opposé à celui du substrat ; et d) recuire à une température adaptée à transformer la couche de silicium amorphe en une couche (43) cristallisée.

    65.
    发明专利
    未知

    公开(公告)号：DE69935472D1

    公开(公告)日：2007-04-26

    申请号：DE69935472

    申请日：1999-06-03

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： MARTY MICHEL ,  CHANTRE ALAIN ,  SCHWARTZMANN THIERRY

    IPC: H01L21/331 ,  H01L29/73 ,  H01L21/265 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737

    Abstract: Selective doping of the intrinsic collector of a vertical bipolar transistor comprises high energy dopant implantation before epitaxy and lower energy and lower dose dopant implantation after epitaxy of a silicon germanium heterojunction base. Selective doping of the intrinsic collector of a vertical bipolar transistor is carried out by (a) forming the intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate; (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well; (c) effecting a first dopant implantation in the intrinsic collector through a first implantation window above the intrinsic collector; (d) forming a silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a silicon and silicon germanium multilayer (8); and (e) effecting a second lower energy and lower dose dopant implantation in the intrinsic collector across the multilayer in a second implantation window located within the first implantation window above the multilayer (8) and self-aligned with the emitter.

    66.
    发明专利
    未知

    公开(公告)号：FR2839811A1

    公开(公告)日：2003-11-21

    申请号：FR0205965

    申请日：2002-05-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： DELPECH PHILIPPE ,  CREMER SEBASTIEN ,  MARTY MICHEL

    IPC: H01L21/02 ,  H01L23/522 ,  H01L21/334 ,  H01L29/94

    Abstract: Capacitor is manufactured in substrate (1) by digging recess into substrate; forming first conformal layer of insulating material; forming second conductive layer; forming third layer of conductive or insulating material filling up recess; digging trenches into third layer, across entire height; depositing fourth layer of conductive material; forming fifth layer of dielectric material; and depositing sixth layer of conductive material. An Independent claim is also included for a capacitor formed in a substrate comprising: (a) a recess (2) dug into a substrate; (b) a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; (c) a second layer of a conductive material covering the first layer; (d) a third layer of a conductive or insulating material filling the recess; (e) trenches crossing the third layer; (f) a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges; (g) a fifth layer of a dielectric material covering the fourth layer; and (h) a sixth layer of a conductive material covering the fifth layer.

    69.
    发明专利
    未知

    公开(公告)号：FR2799048B1

    公开(公告)日：2003-02-21

    申请号：FR9911895

    申请日：1999-09-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  BAUDRY HELENE

    IPC: H01L29/73 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/331 ,  H01L29/737 ,  H01L21/00 ,  H01L21/22 ,  H01L29/732

    Abstract: Bipolar transistor fabrication includes a step of producing a base region (8) comprising an extrinsic base (800) and an intrinsic base, and a step of producing an emitter block having a narrower lower part located in an emitter-window above the intrinsic base. Production of the extrinsic base (800) involves dopant implantation after defining the emitter-window, on both sides at a determined distance from the lateral limits of the emitter-window, with self-alignment about the emitter-window, and before emitter block formation. An oxide block (13) is formed on an insulating layer located above the intrinsic base. The oxide block (13) has a narrower lower part (130) located in an etched hole of the insulating layer and whose dimensions correspond to those of the emitter-window, and an upper wider part (131) resting on the insulating layer. The lateral sides of the etched hole of the insulating layer are self-aligned with the lateral sides (FV) of the upper part of the oxide block. Ion implantation of the extrinsic base is formed on both sides of the upper part of the oxide block (13).

    70.
    发明专利
    未知

    公开(公告)号：FR2813707B1

    公开(公告)日：2002-11-29

    申请号：FR0011419

    申请日：2000-09-07

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUTARTRE DIDIER ,  CHANTRE ALAIN ,  MARTY MICHEL ,  JOUAN SEBASTIEN

    IPC: H01L21/331 ,  H01L29/10 ,  H01L21/28

    Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

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