公开(公告)号：FR2833106B1

公开(公告)日：2005-02-25

申请号：FR0115594

申请日：2001-12-03

Applicant: ST MICROELECTRONICS SA

Inventor： FARCY ALEXIS ,  CORONEL PHILIPPE ,  ANCEY PASCAL ,  TORRES JOAQUIM

IPC: B81B7/00 ,  B81C3/00 ,  H01L21/50 ,  H01L21/56 ,  B81C1/00

Abstract: The circuit includes a first semiconductor substrate supporting the electronic circuit, and a second substrate carrying an electromechanical component. The two substrates are glued together forming a sealed and protective enclosure for the auxiliary component. The first phase of manufacture includes forming the semiconductor chip (PC) within a first substrate, and forming a cavity in the upper surface of this substrate to accommodate an auxiliary component. A wall remains around the cavity, leaving the cavity as a well. The second phase includes formation of the auxiliary component (CAX) on a second semiconductor substrate (SB2), separate from the first. The second substrate is then turned over and applied to the first substrate as a lid with the auxiliary component hanging within the cavity of the first substrate. The two substrates are glued together forming a sealed and protective enclosure for the auxiliary component.

公开(公告)号：FR2858876A1

公开(公告)日：2005-02-18

申请号：FR0350425

申请日：2003-08-12

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： CORONEL PHILIPPE ,  LAPLANCHE YVES ,  PAIN LAURENT

IPC: G03F7/11 ,  G03F7/20 ,  G03F7/36 ,  G03F7/40 ,  H01L21/027 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L21/3065 ,  H01L21/76

公开(公告)号：FR2852441A1

公开(公告)日：2004-09-17

申请号：FR0303194

申请日：2003-03-14

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  MAZOYER PASCALE ,  SKOTNICKI THOMAS

IPC: G11C7/00 ,  G11C11/34 ,  G11C13/00 ,  H01L21/18 ,  H01L27/10 ,  H01L27/105

Abstract: The memory device has a memory cell (CM) with a membrane (MB) fixed on a substrate (SB). A deformable part (PDF) is situated at a distance to the substrate and is deformable between two stable mechanical positions corresponding to two logic levels of the memory cell. A deformation unit (MDF) is deforms the membrane. A detection unit (MDT) detects the logic level of the memory cell. Independent claims are also included for the following: (a) an integrated circuit (b) a method of controlling a logic level of a memory cell.

公开(公告)号：FR2826507B1

公开(公告)日：2004-07-02

申请号：FR0108192

申请日：2001-06-21

Applicant: ST MICROELECTRONICS SA

Inventor： FERREIRA PAUL ,  CORONEL PHILIPPE

IPC: H01L21/033 ,  H01L21/266 ,  H01L21/301 ,  H01L21/8238

公开(公告)号：FR2928490A1

公开(公告)日：2009-09-11

申请号：FR0851494

申请日：2008-03-07

Applicant: ST MICROELECTRONICS SA

Inventor： COUDRAIN PERCEVAL ,  CORONEL PHILIPPE ,  MARTY MICHEL ,  BOPP MATTHIEU

IPC: H01L21/00 ,  H01L31/0232

Abstract: L'invention concerne une structure semiconductrice comprenant une première zone active (R) sous laquelle est enterrée une première couche réfléchissante (32) et au moins une deuxième zone active (G) sous laquelle est enterrée une deuxième couche réfléchissante (34), caractérisée en ce que la surface supérieure de la deuxième couche réfléchissante est plus proche de la surface supérieure de la structure que la surface supérieure de la première couche réfléchissante.

公开(公告)号：FR2860919B1

公开(公告)日：2009-09-11

申请号：FR0350665

申请日：2003-10-09

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： MONFRAY STEPHANE ,  HALIMAOUI AOMAR ,  CORONEL PHILIPPE ,  LENOBLE DAMIEN ,  FENOUILLET BERANGER CLAIRE

IPC: H01L21/762 ,  H01L21/336

Abstract: A region of monocrystalline silicon (20, 124 - 128) on insulator on silicon (24, 120) is destined to receive at least one component. The insulator (26) comprises some over-thickness (OT). Independent claims are also included for: (a) a component realised in such a region of monocrystalline silicon; (b) the fabrication of a semiconductor on insulator region; (c) the fabrication of a MOS transistor.

公开(公告)号：FR2858876B1

公开(公告)日：2006-03-03

申请号：FR0350425

申请日：2003-08-12

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： CORONEL PHILIPPE ,  LAPLANCHE YVES ,  PAIN LAURENT

IPC: G03F7/11 ,  H01L21/3065 ,  G03F7/20 ,  G03F7/36 ,  G03F7/40 ,  H01L21/027 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/76 ,  H01L21/768 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

公开(公告)号：FR2860919A1

公开(公告)日：2005-04-15

申请号：FR0350665

申请日：2003-10-09

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： MONFRAY STEPHANE ,  HALIMAOUI AOMAR ,  CORONEL PHILIPPE ,  LENOBLE DAMIEN ,  FENOUILLET BERANGER CLAIRE

IPC: H01L21/762 ,  H01L21/336

Abstract: A region of monocrystalline silicon (20, 124 - 128) on insulator on silicon (24, 120) is destined to receive at least one component. The insulator (26) comprises some over-thickness (OT). Independent claims are also included for: (a) a component realised in such a region of monocrystalline silicon; (b) the fabrication of a semiconductor on insulator region; (c) the fabrication of a MOS transistor.

公开(公告)号：FR2857150A1

公开(公告)日：2005-01-07

申请号：FR0307960

申请日：2003-07-01

Applicant: ST MICROELECTRONICS SA

Inventor： JACQUET FRANCOIS ,  CANDELLIER PHILIPPE ,  CERUTTI ROBIN ,  CORONEL PHILIPPE ,  MAZOYER PASCALE

IPC: G11C11/405 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  G11C11/401 ,  H01L21/8242

Abstract: The unit has a pair of cells (C1, C2) for storing two independent bits and including field effect transistors with grid (4, 14), respectively. A channel is arranged in a source zone (102), and the two transistors are arranged in between the source zone and a drain zone. An electrode of single polarization (24) is arranged between intermediate portions (1, 11) of the two transistors. An independent claim is also included for a method for manufacturing an integrated DRAM on a surface of a substrate.

公开(公告)号：FR2845522A1

公开(公告)日：2004-04-09

申请号：FR0212278

申请日：2002-10-03

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  CORONEL PHILIPPE ,  LEVERD FRANCOIS

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/417 ,  H01L29/732 ,  H01L21/74

Abstract: An integrated circuit incorporates a buried layer of the type with conductivity determined in a plane essentially parallel to a plane of a main surface of the circuit. The median part of this buried layer (23, 24) is filled with a metallic type material (29). An Independent claim is also included for a method for the formation of a layer buried in a semiconductor substrate of an integrated circuit.