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    61.
    发明专利
    未知

    公开(公告)号：AT449424T

    公开(公告)日：2009-12-15

    申请号：AT03709915

    申请日：2003-01-31

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  DRAY CYRILLE ,  FOURNEL RICHARD ,  POIRIER SEBASTIEN ,  CASPAR DANIEL ,  CANDELIER PHILIPPE

    IPC: H01L29/788 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

    Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

    63.
    发明专利
    未知

    公开(公告)号：DE60219100D1

    公开(公告)日：2007-05-10

    申请号：DE60219100

    申请日：2002-05-06

    Applicant: ST MICROELECTRONICS SA

    Inventor： DRAY CYRILLE ,  FOURNEL RICHARD ,  THOMAS SIGRID

    IPC: G11C16/04

    Abstract: A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the ouput signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.

    64.
    发明专利
    未知

    公开(公告)号：DE60301119D1

    公开(公告)日：2005-09-01

    申请号：DE60301119

    申请日：2003-12-08

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE ,  CANDELIER PHILIPPE ,  JACQUET FRANCOIS

    IPC: G11C14/00 ,  G11C17/14

    Abstract: The memory cell (10) comprises two inverter circuits (14,16) interconnected between the data nodes (N1,N2) so to form a memory circuit (12), two programming transistors (28,30) for implementing an irreversible degradation of the gate oxide layers of transistors (18,18'), and two transistors (32,34) for implementing the functioning of the memory cell after programming. Each inverter circuit (14,16) comprises supplementary MOS transistors (18,20;18',20') connected in series between a supply voltage source (VDD) and the ground circuit (22). Each inverter circuit comprises a p-MOS transistor (18,18') and an n-MOS transistor (20,20'), and the data nodes (N1,N2) are formed between the two transistors, n-MOS and p-MOS. The degraded MOS transistor is a transistor with thin gate oxide layer (GO1). The oxide layer is degraded at least locally so to obtain a variation of current through the transistor at the time of reading the cell. The programming transistors (28,30), or the diodes, are connected between the programming control line (PROG) and the transistors of the inverter circuits. The n-MOS programming transistors (28,30) ensure a selective connection of the gates of the transistors (18,18') to a programming voltage (VREF) at a level sufficient to cause the degradation of the gate oxide layers of the transistors. The inverter circuits are interconnected by the intermediary of a n-MOS transistor (32,34) connected to the control line (SRAM) of functioning the cell as the SRAM cell. The drain and the source electrodes of the transistors (32,34) are connected to the gates of the transistors of the inverter circuits.

    Memory element with a definite number of write cycles, comprises memory units of programmable read-only memory (PROM) type controlled by a chain of selection units
    65.
    发明专利
    Memory element with a definite number of write cycles, comprises memory units of programmable read-only memory (PROM) type controlled by a chain of selection units 未知

    公开(公告)号：FR2840443A1

    公开(公告)日：2003-12-05

    申请号：FR0206863

    申请日：2002-06-04

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  SCHOELLKOPF JEAN PIERRE ,  CANDELIER PHILIPPE

    IPC: G11C8/12 ,  G11C16/08 ,  G11C7/22

    Abstract: The memory element comprises a set of n memory units (10-1,....,10-n), each with an address bus, a data bus, and a control bus connected respectively to the main address bus, the main data bus and the main control bus. The memory units comprise the elements of fuse/antifuse type allowing an irreversible registering of information. The control chain comprises the selection units (12-1,....,12-n) each generating a selection signal, that is a Chip-Select (CSi), where i is from 1 to n, for one of the memory units (10i) in a manner to allow an exclusive access to the selected memory unit. The selection units switch automatically the selection of memory units following the detection of a predetermined condition. The memory element allows to implement an equivalent of a programmable memory of the type few times programmable (FTP), and in particular of type FLASH. A memory circuit (claimed) comprises the memory units of programmable type. The memory element comprises the programmable memory units (10-1,...,10-n) each receiving a Status Bit (SBi) which allows to store an information on the end of selection, and the predetermined condition corresponds to writing the Status Bit in the respective memory unit. The selection units are connected in a chain which allows to compute the selection signal for the memory unit of rank i, and two selection signals, direct and inverse, S(i) and SN(i), are transmitted and received by the selection unit of rank i+1. The selection unit is in two embodiments. In the first embodiment, teh selection unit comprises a bistable of type D, an inverter, and three AND gates. In the second embodiment, the selection unit comprises an inverter and a NOR gate. Each memory unit is implemented by a technology of type CMOS, and the fusible elements are constituted by capacitors with thin oxide layers.

    66.
    发明专利
    未知

    公开(公告)号：FR2823900B1

    公开(公告)日：2003-08-15

    申请号：FR0105343

    申请日：2001-04-20

    Applicant: ST MICROELECTRONICS SA

    Inventor： DRAY CYRILLE ,  FOURNEL RICHARD

    IPC: G11C16/04 ,  H01L27/115 ,  H01L29/66

    Abstract: An FAMOS memory includes memory cells, with each memory cell including an insulated gate transistor, and a first access transistor having a drain connected to a source of the insulated gate transistor. The FAMOS memory also includes an insulation transistor having a drain and a source respectively connected to the source of the insulated gate transistors of two adjacent cells of a same row. Each insulated gate transistor has a ring structure, and a ladder-shaped separation region insulates the cells of the same row.

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