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    62.
    发明专利
    未知

    公开(公告)号：DE602006009662D1

    公开(公告)日：2009-11-19

    申请号：DE602006009662

    申请日：2006-08-24

    Applicant: ST MICROELECTRONICS SRL ,  HYNIX SEMICONDUCTOR INC

    Inventor： MICHELONI RINO ,  CRIPPA LUCA ,  RAVASIO ROBERTO ,  PIO FEDERICO

    IPC: G11C16/34

    Abstract: A method for operating a flash memory device ( 100 ) is proposed. The memory device includes a matrix of memory cells ( 110 ) each one having a programmable threshold voltage (V T ) defining a value stored in the memory cell. The method includes the steps of crasing a block ( 115 ) of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell (110 0e ) of the block for writing a target value; restoring the threshold voltage of a subset (110 0e ; 110 1o ) of the memory cells of the block to the compacting range, the subset consisting of the at least one first memory cell (110 0e ) and/or at least one second memory cell of the block (110 1o ) being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

    63.
    发明专利
    未知

    公开(公告)号：DE602006006788D1

    公开(公告)日：2009-06-25

    申请号：DE602006006788

    申请日：2006-03-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARELLI ALESSIA ,  INTINI VALERIA ,  RAVASIO ROBERTO ,  MICHELONI RINO

    IPC: G06F11/10 ,  G06F11/14

    Abstract: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A 0 , A 1 , ..., A LS-1 ) to generate a first recovered string (S 1 ), and performing a first decoding attempt using the first recovered string (S 1 ). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S 2 -S N ) is generated. On the basis of a comparison between the first recovered string (S 1 ) and the second recovered string (S 2 -S N ), a modified string (S M ) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (S M ).

    65.
    发明专利
    未知

    公开(公告)号：DE69937559T2

    公开(公告)日：2008-10-23

    申请号：DE69937559

    申请日：1999-09-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  SACCO ANDREA ,  MOGNONI SABINA

    IPC: G01R31/02 ,  G11C29/00 ,  G01R31/28 ,  G01R31/30 ,  G01R31/319 ,  G11C17/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50

    Abstract: The non volatile memory device integrates, in one and the same chip (100), the array (2) of memory cells, a voltage regulator (REG) which supplies a regulated operating voltage (Vr) to a selected word line (LWL1), and a short circuit detecting circuit (10). The short circuit detecting circuit detects the output voltage (IM1) of the voltage regulator (REG), which is correlated to the current (Iw) for biasing the cells (3) of the word line selected (LWL1). Once settled to the steady state condition, the output current (IM1) assumes one first value (IM1') in the absence of short circuits, and one second value (IM1") in the presence of a short circuit between the word line selected (LWL1) and one or more adjacent word lines (LWL0, LWL2, ..., LWLn). The short circuit detecting circuit (10) compares the output current (IM1) of the voltage regulator (REG) with a reference value (Iref) and generates at output a short circuit digital signal (Vo) which indicates the presence or otherwise of a short circuit.

    67.
    发明专利
    未知

    公开(公告)号：DE60129928D1

    公开(公告)日：2007-09-27

    申请号：DE60129928

    申请日：2001-04-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI

    IPC: G11C11/56 ,  G11C7/06 ,  G11C7/22 ,  G11C16/28 ,  G11C16/32

    Abstract: The method for timing reading of a memory cell envisages supplying the memory cell (10) with a constant current (I) by means of a first capacitive element (23), integrating said current (I) in a time interval ( DELTA t), and controlling the duration of the time interval ( DELTA t) in such a way as to compensate for any deviations in the current (I) from a nominal value. In particular, a reference current (IR) is supplied to a reference cell (101) by means of a second capacitive element (122); next, a first voltage (Var) present on the second capacitive element (122) is measured; finally, the memory cell (10) is deactivated when the first voltage (Var) is equal to a second voltage (Vref), which is constant.

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