公开(公告)号：DE69519476T2

公开(公告)日：2001-06-28

申请号：DE69519476

申请日：1995-12-07

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： CAPOCELLI PIERO ,  ZAMBRANO RAFFAELE ,  PIO FEDERICO ,  RIVA CARLO

IPC: H01F17/00 ,  H01F41/04 ,  H01L23/522 ,  H01L27/04

Abstract: Inductive structures making highly efficient use of the magnetic flux generated, and being consistent with integrated circuit manufacturing techniques, and a method of making them on a semiconductor substrate concurrently with the formation of the integrated circuit itself.

公开(公告)号：DE69327320T2

公开(公告)日：2000-05-31

申请号：DE69327320

申请日：1993-09-30

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78

Abstract: An integrated structure active clamp for the protection of a power device against overvoltages comprises a plurality of serially connected diodes (D1-D4,SD1-D4,DF1,DF2), each having a first and a second electrodes, obtained in a lightly doped epitaxial layer (2;2,2') of a first conductivity type in which the power device (M) is also obtained; a first diode (D1;SD1) of said plurality of diodes has the first electrode (12,13;31,32) connected to a gate layer (7) of the power device (M) and the second electrode (14,15;35) connected to the second electrode (16,17;21,22;27,52,28) of at least one second diode (D2-D4) of the plurality whose first electrode (18,20,24,29) is connected to a drain region (D) of the power device (M); said first diode (D1;SD1) has its first electrode (12,13;31,32) comprising a heavily doped contact region (12;32) of the first conductivity type included in a lightly doped epitaxial layer region (13;31) of the first conductivity type which is isolated from said lightly doped epitaxial layer (2;2,2') by means of a buried region (14;33) of a second conductivity type and by a heavily doped annular region (15;34) of the second conductivity type extending from a semiconductor top surface to said buried region (14;33).

公开(公告)号：DE69512021T2

公开(公告)日：2000-05-04

申请号：DE69512021

申请日：1995-03-31

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L29/08 ,  H01L29/739 ,  H01L29/78

Abstract: A DMOS device structure comprises a lightly doped semiconductor layer (1) of a first conductivity type, a plurality of lightly doped semiconductor regions (4,13,18) of a second conductivity type extending from a top surface of the lightly doped semiconductor layer (1) thereinto, source regions (6,16) of the first conductivity type contained in the lightly doped semiconductor regions (4,13,18) and defining channel regions. The lightly doped semiconductor regions (4,13,18) are contained in respective enhancement regions (12,14,19) of the lightly doped semiconductor layer of the same conductivity type as but with a lower resistivity than the lightly doped semiconductor layer (1).

公开(公告)号：DE69512021D1

公开(公告)日：1999-10-14

申请号：DE69512021

申请日：1995-03-31

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L29/08 ,  H01L29/739 ,  H01L29/78

Abstract: A DMOS device structure comprises a lightly doped semiconductor layer (1) of a first conductivity type, a plurality of lightly doped semiconductor regions (4,13,18) of a second conductivity type extending from a top surface of the lightly doped semiconductor layer (1) thereinto, source regions (6,16) of the first conductivity type contained in the lightly doped semiconductor regions (4,13,18) and defining channel regions. The lightly doped semiconductor regions (4,13,18) are contained in respective enhancement regions (12,14,19) of the lightly doped semiconductor layer of the same conductivity type as but with a lower resistivity than the lightly doped semiconductor layer (1).

公开(公告)号：DE69325994D1

公开(公告)日：1999-09-16

申请号：DE69325994

申请日：1993-05-19

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L27/06 ,  H01L27/02 ,  H01L27/04 ,  H01L27/08 ,  H01L29/78 ,  H01L29/772

Abstract: An integrated structure current sensing resistor for a power MOS device consists of a doped region (20,21,50) extending from a deep body region (2) of at least one cell (1a) of a first plurality of cells, constituting a main power device, to a deep body region (2) of a corresponding cell (1b) of a second smaller plurality of cells constituting a current sensing device.

公开(公告)号：IT1252623B

公开(公告)日：1995-06-19

申请号：ITMI913265

申请日：1991-12-05

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： PAPARO MARIO ,  ZAMBRANO RAFFAELE

IPC: H01L29/78 ,  H01L21/76 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L

Abstract: In the device there are present a first, second and third switch designed to connect a node of the insulation region with a ground node, the collector or drain of the power transistor and a region of a control circuit transistor respectively. The dynamic insulation circuit of the control circuit comprises a pilot circuit which controls: closing of the first switch when the potential of the ground node (or insulation region) is less than the potential of the collector or drain region of the power transistor and the potential of the control circuit region, closing of the second switch and opening of the first when the potential of the collector or drain region of the power transistor is less than the potential of the ground node (or the insulation region), closing of the third switch and opening of the first when the potential of said control circuit region is less than the potential of the ground node (or the insulation region).

公开(公告)号：IT1246759B

公开(公告)日：1994-11-26

申请号：IT2257790

申请日：1990-12-31

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： PUZZOLO SANTO ,  ZAMBRANO RAFFAELE ,  PAPARO MARIO

IPC: H01L21/8249 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L

Abstract: In the version with unisolated components the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer; the low voltage bipolar transistor is indeed situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In the version with isolated components, in an n- epitaxial layer there are two p+ regions, i.e. the first, constituting the power transistor base, encloses the n+ emitter region of said transistor while the second encloses two n+ regions and one p+ region constituting the collector, emitter and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.

公开(公告)号：DE60140757D1

公开(公告)日：2010-01-21

申请号：DE60140757

申请日：2001-12-28

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE ,  ARTONI CESARE

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/8246 ,  H01L29/51

Abstract: A memory cell (30) of a stacked type is formed by a MOS transistor (32) and a ferroelectric capacitor (33). The MOS transistor (32) is formed in an active region (40) of a substrate (30) of semiconductor material and comprises a conductive region (34a). The ferroelectric capacitor (33) is formed on top of the active region and comprises a first and a second electrodes (45, 47) separated by a ferroelectric region (46). A contact region (44a) connects the conductive region (34a) of the MOS transistor to the first electrode (45) of the ferroelectric capacitor (33). The ferroelectric capacitor (33) has a non-planar structure, formed by a horizontal portion (45) and two side portions (48) extending transversely to, and in direct electrical contact with, the horizontal portion.

公开(公告)号：DE69739202D1

公开(公告)日：2009-02-26

申请号：DE69739202

申请日：1997-11-14

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/285

公开(公告)号：IT1320408B1

公开(公告)日：2003-11-26

申请号：ITTO20000543

申请日：2000-06-06

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE

IPC: G11C17/12

Abstract: The ROM memory cell, not decodable by visual inspection comprises a substrate of semiconductor material having a first conductivity type, in particular P-. A first MOS device having a first threshold voltage is formed in a first portion of the substrate, and a MOS device having a second threshold voltage, greater than the first threshold voltage, is formed in a second portion of the substrate adjacent to the first portion. The second MOS device is a diode reverse biased during a reading phase of the ROM memory cell and comprises a source region having the first conductivity type and a drain region having a second conductivity type. The source region has a level of doping higher than that of the substrate.