公开(公告)号：US10064275B1

公开(公告)日：2018-08-28

申请号：US15652276

申请日：2017-07-18

Applicant: Mellanox Technologies, Ltd.

Inventor： Haim Peretz ,  Moshe Shoval

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/40 ,  H05K1/02

CPC classification number: H05K1/111 ,  H05K1/0271 ,  H05K1/09 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/09218 ,  H05K2201/10636 ,  H05K2201/10727 ,  Y02P70/611 ,  Y02P70/613

Abstract: A circuit board includes a substrate and multiple pads. The multiple pads are disposed on the substrate and have respective footprints for connecting one or more electronic components to the circuit board, at least a padfrom among the pads includes a linear electrical trace laid out in a two-dimensional (2D) pattern that covers at least a part of a footprint of the pad.

公开(公告)号：US09999125B2

公开(公告)日：2018-06-12

申请号：US15602137

申请日：2017-05-23

Applicant: HE BEI SINOPACK ELECTRONIC TECH CO., LTD.

Inventor： Dongliang Zhao ,  Fei Ding ,  Linjie Liu

IPC: H05K1/09 ,  H05K1/03 ,  H05K1/02 ,  H05K3/40 ,  H05K3/18 ,  H05K3/00 ,  H05K1/11

CPC classification number: H05K1/0306 ,  H01L23/13 ,  H05K1/0213 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/005 ,  H05K3/188 ,  H05K3/40 ,  H05K3/4038 ,  H05K3/4617 ,  H05K2201/0723 ,  H05K2201/09218 ,  H05K2201/09618 ,  H05K2201/10303

Abstract: The present application discloses a method for fabricating ceramic insulator for electronic packaging, and relates to a technical field of outer shell packaging of electronic devices. Under the circumstance of using neither a chemical coating nor any bonding wire connection circuit, through a design that builds a electroplated circuit into the ceramic insulator, the method accomplishes coating of a nickel alloy protection layer onto a porcelain by an electroplating method, so that not only quality of a coating layer but also requirement of a complete appearance can be ensured. All circuits of the ceramic insulator fabricated by the aforesaid method can conduct with external circuits, such that the electroplating method can be used to accomplish coating of the nickel alloy layer, after accomplishment of all metal coating, metallization parts on an end surface of the porcelain is removed.

公开(公告)号：US20170271733A1

公开(公告)日：2017-09-21

申请号：US15614640

申请日：2017-06-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru KATO ,  Satoshi ISHINO ,  Jun SASAKI ,  Kuniaki YOSUI ,  Takahiro BABA ,  Nobuo IKEMOTO

IPC: H01P3/02 ,  H01P3/08 ,  H01P5/00 ,  H05K1/02 ,  H05K1/14 ,  H01P5/02 ,  H05K3/36

CPC classification number: H01P3/02 ,  H01P3/003 ,  H01P3/026 ,  H01P3/08 ,  H01P3/082 ,  H01P3/085 ,  H01P5/00 ,  H01P5/028 ,  H05K1/0218 ,  H05K1/0221 ,  H05K1/0237 ,  H05K1/0242 ,  H05K1/025 ,  H05K1/028 ,  H05K1/0296 ,  H05K1/14 ,  H05K1/148 ,  H05K1/186 ,  H05K3/361 ,  H05K2201/0707 ,  H05K2201/09218

Abstract: A transmission line portion of a flat cable includes first regions and second regions connected alternately. In the first region, the transmission line portion is a flexible tri-plate transmission line including a dielectric element including a signal conductor, a first ground conductor including opening portions, and a second ground conductor which is a solidly filled conductor. In the second region, the transmission line portion is a hard tri-plate transmission line including a wide dielectric element including a meandering conductor, and a first ground conductor and a second ground conductor which are solidly filled conductors. A variation width of the characteristic impedance in the second region is larger than a variation width of the characteristic impedance in the first region.

公开(公告)号：US20170064821A1

公开(公告)日：2017-03-02

申请号：US14840979

申请日：2015-08-31

Applicant: Kristof Darmawikarta ,  Daniel Sobieski ,  Kyu Oh Lee ,  Sri Ranga Sai Boyapati

Inventor： Kristof Darmawikarta ,  Daniel Sobieski ,  Kyu Oh Lee ,  Sri Ranga Sai Boyapati

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/40 ,  H05K3/18 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/113 ,  H05K3/0041 ,  H05K3/181 ,  H05K3/188 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09218 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/096 ,  H05K2201/09654 ,  H05K2203/0548

Abstract: Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.

Abstract translation: 一些示例形式涉及电子包装。 电子封装包括第一电介质层，其包括形成在第一电介质层的表面上的电迹线和在第一电介质层的表面上的第二电介质层。 第二电介质层包括开口。 电迹线在开口内。 电子封装包括电互连，其填充开口并且在第二电介质层的上表面上方延伸，使得电互连电连接到第一电介质层上的电迹线。

公开(公告)号：US09570383B2

公开(公告)日：2017-02-14

申请号：US14746247

申请日：2015-06-22

Applicant: Jin-Kyung Kim ,  Yong-hoon Kim ,  Seong-Ho Shin

Inventor： Jin-Kyung Kim ,  Yong-hoon Kim ,  Seong-Ho Shin

IPC: H01L23/02 ,  H01L23/498 ,  H05K1/18 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49838 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/181 ,  H05K2201/09218 ,  H05K2201/10378 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Semiconductor packages, module substrates and semiconductor package modules having the same are provided. The semiconductor package module includes a module substrate provided with a plurality of signal wires on an upper surface thereof, a package substrate disposed on the module substrate, a semiconductor chip disposed on one surface of the package substrate, and a plurality of external connection terminals disposed on another surface of the package substrate.

Abstract translation: 提供半导体封装，模块基板和具有该半导体封装的半导体封装模块。 半导体封装模块包括在其上表面上设置有多个信号线的模块基板，设置在模块基板上的封装基板，设置在封装基板的一个表面上的半导体芯片，以及设置在多个外部连接端子 在封装衬底的另一个表面上。

公开(公告)号：US09490516B2

公开(公告)日：2016-11-08

申请号：US14564140

申请日：2014-12-09

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru Kato ,  Satoshi Ishino ,  Jun Sasaki ,  Kuniaki Yosui ,  Takahiro Baba ,  Nobuo Ikemoto

IPC: H01P3/08 ,  H05K1/02 ,  H05K1/14 ,  H05K3/36 ,  H01P5/02

CPC classification number: H01P3/02 ,  H01P3/003 ,  H01P3/026 ,  H01P3/08 ,  H01P3/082 ,  H01P3/085 ,  H01P5/00 ,  H01P5/028 ,  H05K1/0218 ,  H05K1/0221 ,  H05K1/0237 ,  H05K1/0242 ,  H05K1/025 ,  H05K1/028 ,  H05K1/0296 ,  H05K1/14 ,  H05K1/148 ,  H05K1/186 ,  H05K3/361 ,  H05K2201/0707 ,  H05K2201/09218

Abstract: A transmission line portion of a flat cable includes first regions and second regions connected alternately. In the first region, the transmission line portion is a flexible tri-plate transmission line including a dielectric element including a signal conductor, a first ground conductor including opening portions, and a second ground conductor which is a solidly filled conductor. In the second region, the transmission line portion is a hard tri-plate transmission line including a wide dielectric element including a meandering conductor, and a first ground conductor and a second ground conductor which are solidly filled conductors. A variation width of the characteristic impedance in the second region is larger than a variation width of the characteristic impedance in the first region.

Abstract translation: 扁平电缆的传输线部分包括交替连接的第一区域和第二区域。 在第一区域中，传输线部分是包括具有信号导体的介质元件，包括开口部分的第一接地导体和作为固体填充导体的第二接地导体的柔性三板传输线。 在第二区域中，传输线部分是包括具有曲折导体的宽电介质元件和固体填充导体的第一接地导体和第二接地导体的硬三板传输线。 第二区域中的特性阻抗的变化幅度大于第一区域中的特性阻抗的变化宽度。

公开(公告)号：US20140325995A1

公开(公告)日：2014-11-06

申请号：US14245221

申请日：2014-04-04

Applicant: ROLLS-ROYCE PLC

Inventor： Claudio ZIZZO

IPC: H05K1/02

CPC classification number: H05K1/0298 ,  C08K3/04 ,  C08K7/06 ,  F01D5/282 ,  F01D17/24 ,  F01D25/24 ,  F02C7/00 ,  F05D2300/224 ,  F05D2300/50 ,  F05D2300/6012 ,  F05D2300/603 ,  F05D2300/614 ,  H05K2201/09218 ,  Y02T50/672 ,  Y02T50/673

Abstract: A composite structure is provided. The structure is formed of rigid composite material in which non-metallic continuous fibres reinforce a polymer matrix. The continuous fibres are electrically conductive. The structure has electrodes electrically connected to the continuous fibres. The composite material contains one or more insulating barriers which electrically divide the structure so that a first portion of the material in electrical contact with one of the electrodes can be held at a different electrical potential to a second portion of the material in electrical contact with the other electrode. In use, an electrical unit can be provided to electrically bridge the first and second portions of the material such that electrical signals can be transmitted between the electrodes and the electrical unit via the continuous fibres.

Abstract translation: 提供复合结构。 该结构由刚性复合材料形成，其中非金属连续纤维增强聚合物基体。 连续纤维是导电的。 该结构具有电连接到连续纤维的电极。 复合材料包含一个或多个绝缘屏障，其将结构电分开，使得与电极之一电接触的材料的第一部分可以保持在与第二部分电接触的材料的不同电位 其他电极。 在使用中，可以提供电气单元以电气地桥接材料的第一和第二部分，使得电信号可以经由连续纤维在电极和电气单元之间传递。

公开(公告)号：US20240339381A1

公开(公告)日：2024-10-10

申请号：US18130582

申请日：2023-04-04

Applicant: Intel Corporation

Inventor： Hiroki TANAKA ,  Veronica STRONG ,  Henning BRAUNISCH ,  Haobo CHEN ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Brandon C. MARIN

IPC: H01L23/482 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L23/4821 ,  H01L21/76831 ,  H01L23/49827 ,  H01L23/49866 ,  H01L21/30604 ,  H05K2201/09218

Abstract: Embodiments disclosed herein include an interposer. In an embodiment, the interposer comprises a substrate, where the substrate comprises a glass layer. In an embodiment, a trace is on the substrate, where the trace has a bottom surface, sidewall surfaces, and a top surface. In an embodiment, the sidewall surfaces and the top surface are exposed to air. In an embodiment, a trench into the substrate is adjacent to at least one sidewall surface of the trace.

公开(公告)号：US20180206341A1

公开(公告)日：2018-07-19

申请号：US15869169

申请日：2018-01-12

Applicant: Commissariat a l'energie atomique et aux energies alternatives

Inventor： Mohammed BENWADIH

IPC: H05K3/10 ,  B29C51/14 ,  B29C51/42 ,  B29C51/10 ,  H05K1/09 ,  H05K3/00

CPC classification number: H05K3/10 ,  B29C51/10 ,  B29C51/14 ,  B29C51/421 ,  B29K2105/256 ,  B29K2995/0005 ,  B29L2009/005 ,  B29L2031/3456 ,  H01Q1/38 ,  H05K1/092 ,  H05K3/0014 ,  H05K3/1283 ,  H05K2201/0129 ,  H05K2201/026 ,  H05K2201/0272 ,  H05K2201/09218 ,  H05K2201/10098 ,  H05K2203/0425 ,  H05K2203/1105 ,  H05K2203/1121

Abstract: The device intended to be thermoformed comprises a substrate capable of being thermoformed and an electrically conductive member integral with the said substrate. The electrically conductive member comprises: electrically conductive particles, an electrically conductive material, electrically conductive elements of elongated shape. The electrically conductive material has a melting point which is strictly less than the melting point of the electrically conductive particles and than the melting point of the elements of elongated shape.

公开(公告)号：US09872398B1

公开(公告)日：2018-01-16

申请号：US15231515

申请日：2016-08-08

Applicant: International Business Machines Corporation

Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Phillip V. Mann ,  Kevin M. O'Connell

IPC: H01K3/10 ,  H05K3/42 ,  H05K3/00 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K3/42 ,  H05K1/0216 ,  H05K1/115 ,  H05K3/0047 ,  H05K2201/09218 ,  H05K2201/09545 ,  H05K2201/0959 ,  Y10T29/49165

Abstract: A method and structure are provided for implementing enhanced via creation without creating a via barrel stub. The need to backdrill during printed circuit board (PCB) manufacturing is eliminated. After the vias have been drilled, but before plating, a via plug with a specialized geometry and including a capillary is inserted into each via to allow electroplating on only preferred wall surfaces of the vias. Then a board plating process of the PCB manufacturing is performed.