公开(公告)号：JP2000284466A

公开(公告)日：2000-10-13

申请号：JP2000069197

申请日：2000-03-13

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： CARPI ENIO ,  BUTT SHAHID

IPC: G03F1/00 ,  H01L21/027 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To provide a mask pattern capable of increasing the depth of focus and exposure latitude while maintaining or improving the resolution for the characteristics desired to be imaged. SOLUTION: The surface of a substrate 18 is provided with plural elongated structures 13 which are arranged nearly parallel to each other and plural projecting parts 14 below the resolution which extend transversely into the spaces between these elongated structures from the elongated structures. The plural projecting parts 14 have nearly the same sizes in the direction parallel to the elongated structures 13. The plural projecting parts 14 are periodically arranged apart spaced intervals in the direction parallel to the elongated structures 13. The elongated structures 13 and the projecting parts 14 are formed of energy absorption materials containing at least one among chromium, carbon and molybdenum.

公开(公告)号：JP2000251468A

公开(公告)日：2000-09-14

申请号：JP2000034052

申请日：2000-02-10

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JI BRIAN ,  MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HANSON DAVID

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To increase data speed or band width by arranging a pre-fetch circuit so that data speed among each hierarchy stage is all equalized substantially and controlling a latch so that the respective data speed at each hierarchy stage is all maintained. SOLUTION: Stages A-C have different data speed/signal time (data speed/bit) a, b, c respectively. Data speed at each stage is determined by data speed/signal path (selected by the number of signal path that is the number of pre-fetch). Pre-fetch is constituted between stages A-B of m>=int(a/b), pre-fetch is constituted between stages B-C of n>=int(b/c), and integers m, n are adjusted as desired. In order to vary pre-fetch depth at each stage, a pointer is designed so as to correspond to pre-fetch depth. A pointer signal is supplied by using a control circuit 214, the control circuit 214 latches continuously data made to synchronize with the latch included in a pre-fetch circuit, and timing is performed optimally.

公开(公告)号：JP2000236242A

公开(公告)日：2000-08-29

申请号：JP2000017125

申请日：2000-01-26

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CHU ALBERT M ,  FIFIELD JOHN A ,  ROTELLA JASON E ,  DORTU JEAN-MARC

IPC: H03K5/15 ,  G11C7/22 ,  H03L7/081 ,  H03L7/095

Abstract: PROBLEM TO BE SOLVED: To obtain a circuit which is improved in the timing between input and output pulse trains. SOLUTION: This circuit is equipped with a delay lock loop 32 which has a receiver 33, a pulse generator 36, a logic network 50, and a variable delay line 34, and extract two pulse trains having side edges of the same type from the leading and trailing edges of the input pulse train, selects the time delay degree of the variable delay line, and generates a combined output pulse train which has a predetermined phase relation with the input pulse train.

公开(公告)号：JP2000235786A

公开(公告)日：2000-08-29

申请号：JP2000035922

申请日：2000-02-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  GERD FRANKOVSKI

IPC: G11C7/00 ,  G11C7/10 ,  G11C19/00 ,  G11C19/28 ,  H03K17/22 ,  H03K19/096

Abstract: PROBLEM TO BE SOLVED: To obtain a low voltage bus signalling architecture by providing a storage circuit which stores data after it is placed in a set state, an output circuit which connects stored data to an output by responding to an output strobe pulse and a reset circuit resetting the storage circuit by responding to the falling edge of the output strobe pulse. SOLUTION: This low voltage bus signalling architecture 20 has a driver 200 and a storage part 210. The driver 200 is an n-channel MOSFET inverter and inputs an input logic signal being on a line 203. The storage part 210 has a latch 250, an output circuit 260 and a reset circuit 270. The output circuit 260 connects stored data to an output DQ by responding to an output strobe pulse PNTo1. The reset circuit 270 precharges the storage part 210 via a first transistor 240 by responding to the falling edge of the pulse PNTo1.

公开(公告)号：JP2000222898A

公开(公告)日：2000-08-11

申请号：JP36513699

申请日：1999-12-22

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To increase yield of chips while preventing signal contention of a sense amplifier using a high replacement flexibility redundancy and method. SOLUTION: Redundancy elements are integrated in at least two memory arrays which don't share the sense amplifiers. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block which does not share sense amplifiers with the first block. The corresponding row/column line is replaced to mimic the redundancy replacement of the first block.

公开(公告)号：JP2000208434A

公开(公告)日：2000-07-28

申请号：JP2000000881

申请日：2000-01-06

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： RUPP THOMAS S ,  ALAN THOMAS ,  FRANZ ZACHA

IPC: H01L21/302 ,  G03F7/40 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To form a contact of minimum feature dimensions by forming a pattern with a first parallel line and a second parallel line vertical to it inside a mask layer on a dielectric layer and forming a rectangular hole which reaches a substrate layer inside a dielectric layer according to the pattern. SOLUTION: A dielectric layer 22, a mask layer 24, a mask layer 26 and a resist layer 28 are provided sequentially on a substrate layer 20. The mask layer 26 is etched according to a line 30 of a pattern of the resist layer 28 and a parallel line 27 is formed in the mask layer 26. Then, a resist layer 32 is provided. A pattern of the resist layer 32 comprises a parallel line 34 and the line 34 is vertical to the line 27. A lattice pattern with a rectangular hole 36 is formed by anisotropically etching the mask layer 24 by using the line 27 and the line 34. The dielectric layer 22 is etched until it reaches the substrate layer 20 according to the lattice pattern.

公开(公告)号：JP2000195860A

公开(公告)日：2000-07-14

申请号：JP37512499

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： SCHNABEL RAINER FLORIAN ,  RONALD PHILLIPI ,  HOINKIS MARK ,  WEBER STEFAN ,  ROY IGARUDEN ,  WEIGAND PETER ,  LAWRENCE CLEVENGER

IPC: H01L23/52 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To increase the electromigration lifetime of a semiconductor device by stacking a liner by an ionizing metal plasma physical deposition method, thereby reducing the mass carriage by electromigration. SOLUTION: A dielectric layer is made on a substrate. The dielectric layer is patterned, and a contact hole 26 is made, and conductive material is stacked on a dielectric layer so as to fill the contact hole 26 and cover the dielectric layer. Next, excess material is removed by polishing from the surface 29 so as to make a flat surface for an additional layer. Next, a liner 40 is stacked on the dielectric layer 29. This liner consists of a material having high electromigration resistance. For example, titanium(Ti) and its alloy tantalum(Ta) and its alloy, or TiN or Tan is included as such a liner material. This liner 40 is stacked, using an ionizing metal plasma physical deposition method.

公开(公告)号：JP2000148528A

公开(公告)日：2000-05-30

申请号：JP30895499

申请日：1999-10-29

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： GARREAU OLIVIER

IPC: G06F11/22 ,  G01R31/28 ,  G01R31/3185

Abstract: PROBLEM TO BE SOLVED: To obtain a test device which supports an embedded debugging protocol by providing a programmable switch which forms a test loop between a master controller and a selected integrated circuit. SOLUTION: The programmable switch 204 is connected to a slave target device 206 which includes JTAG-based integrated circuits IC1 to IC4. At least one of the integrated circuits IC1 to IC4 is an on-chip debugging support(OCDS) integrated circuit which has an on-chip debugging circuit. A switch controller 218 included in the master controller 202 sends a switch control signal out and a programmable switch 204 connects one integrated circuit selected out of the ICI to IC4 to a JTAG controller 210. The controller 210 functionally tests, for example, the integrated circuit ICI by using the corresponding JTAG test protocol.

公开(公告)号：JP2002072029A

公开(公告)日：2002-03-12

申请号：JP2001170141

申请日：2001-06-05

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： VAN DOORN SCHELTO

IPC: G02B6/36 ,  G02B6/00 ,  G02B6/38 ,  G02B6/42

Abstract: PROBLEM TO BE SOLVED: To provide an optical fiber connector system that allows direct substrate-vs.-substrate optical communications without needing data transmission through a back plane. SOLUTION: The system is provided with a means for mounting an optical fiber input part 126 on printed boards 14-20, an optical component 130, and an optical fiber receiving surface 144. The optical fiber receiving surface 144 is provided with two or more alignment grooves 146 that receive two or more optical fibers 128 of a multi-fiber optical cable 120 and that are designed to guide the received optical fibers so as to bring them into optical contact with the optical component 130.

公开(公告)号：JP2002016241A

公开(公告)日：2002-01-18

申请号：JP2001126300

申请日：2001-04-24

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： BLANCHARD RICHARD A ,  WHITNEY DAVID L

IPC: H01L27/14 ,  H01L27/04 ,  H01L27/144 ,  H01L29/78 ,  H01L31/10 ,  H01L31/12

Abstract: PROBLEM TO BE SOLVED: To provide an advantageous method of reducing an on-state resistance of a transistor in a semiconductor device 36, including the transistor 38 formed on semiconductor substrates 12, 14, the transistor comprising a first terminal region 16 and a second terminal region 18, the terminal regions forming a current channel 44, when the transistor is conducting. SOLUTION: The semiconductor device 36 comprises a minority carrier injector 40 positioned near the second terminal region, with the minority carrier injector supplying the minority carrier into the transistor, when the transistor is in a prescribed voltage state; and a photoelectric device 42 which generates injection voltage in the minority carrier injector in response to incident light, the injection voltage which drives the transistor into the prescribed voltage state and, thereby causing the injector to supply the minority carrier into the vicinity of the second terminal region.