公开(公告)号：US20210013105A1

公开(公告)日：2021-01-14

申请号：US17037364

申请日：2020-09-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265

Abstract: Semiconductor arrangements and methods of manufacturing the same. The semiconductor arrangement may include: a substrate including a base substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer; first and second fin structures formed on the substrate and extending in the same straight line, each of the first and second fin structures including at least portions of the second semiconductor layer; a first isolation part formed around the first and second fin structures on opposite sides of the straight line; first and second FinFETs formed on the substrate based on the first and second fin structures respectively; and a second isolation part between the first and second fin structures and intersecting the first and second fin structures to isolate the first and second fin structures from each other.

公开(公告)号：US20200335596A1

公开(公告)日：2020-10-22

申请号：US16561192

申请日：2019-09-05

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang YIN ,  Jiaxin YAO ,  Qingzhu ZHANG ,  Zhaohao ZHANG ,  Tianchun YE

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L21/225

Abstract: A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.

公开(公告)号：US10763105B2

公开(公告)日：2020-09-01

申请号：US16234303

申请日：2018-12-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Xinyu Liu ,  Yidan Tang ,  Shengkai Wang ,  Yun Bai ,  Chengyue Yang

IPC: H01L21/02 ,  H01L29/78

Abstract: A method of manufacturing a grooved-gate MOSFET device based on a two-step microwave plasma oxidation, including: etching a grooved gate, and oxidizing silicon carbide on a surface of the grooved gate to silicon dioxide by microwave plasma to form a grooved-gate oxide layer, the step of forming the grooved-gate oxide layer including: placing a silicon carbide substrate subjected to the grooved gate etching in a microwave plasma generating device; introducing a first oxygen-containing gas, heating generated oxygen plasma to a first temperature at a first heating rate, and performing low-temperature plasma oxidation at the first temperature and a first pressure; heating the oxygen plasma to a second temperature at a second heating rate, introducing a second oxygen-containing gas, and performing high-temperature plasma oxidation at the second temperature and a second pressure until a predetermined thickness of silicon dioxide is formed; stopping introduction of the oxygen-containing gas, and completing the reaction.

公开(公告)号：US10720578B2

公开(公告)日：2020-07-21

申请号：US16070485

申请日：2016-04-29

Applicant: THE INSTITUTE OF MICROELECTRONICS OF CHINESE ACADEMY OF SCIENCES

Inventor： Hangbing LV ,  Ming Liu ,  Xiaoxin Xu ,  Qing Luo ,  Qi Liu ,  Shibing Long

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are a self-gating resistive storage device and a method for fabrication thereof; said self-gating resistive storage device comprises: lower electrodes; insulating dielectric layers arranged perpendicular to, and intersecting with, the lower electrodes to form a stacked structure, said stacked structure being provided with a vertical trench; a gating layer grown on the lower electrodes by means of self-alignment technique, the interlayer leakage channel running through the gating layer being isolated via the insulating dielectric layers; a resistance transition layer arranged in the vertical trench and connected to the insulating dielectric layers and the gating layer; and an upper electrode arranged in the resistance transition layer. In the storage device provided by the described technical solution, the gating layer is grown on the lower electrodes by means of self-alignment technique, such that the interlayer leakage channel running through the gating layer is isolated via the insulating dielectric layers; thus leakage between the upper and lower word lines through the gating layer is prevented, solving the technical problem in the prior art of leakage between the upper and lower word lines in a self-gating resistive storage device, and improving the reliability of the device.

公开(公告)号：US20200211910A1

公开(公告)日：2020-07-02

申请号：US16722406

申请日：2019-12-20

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang YIN ,  Qingzhu ZHANG ,  Xiang LIN

IPC: H01L21/84 ,  H01L27/12 ,  H01L23/522

Abstract: A multilayer MOS device and a method for manufacturing the same. The manufacturing method includes: providing a MOS device including n layers, where n is a natural number greater than zero; forming a semiconductor layer on the MOS device including n layers; forming a gate oxide layer and a dummy gate on the semiconductor layer sequentially, where at least a part of the gate oxide layer is located between the dummy gate and the semiconductor layer; forming a metal silicide layer in the semiconductor layer at two sides of the dummy gate, to obtain a MOS device of an (n+1)-th layer, where the metal silicide layer serves as a metallized source-drain region or the metal silicide layer is doped to form a metalized source-drain region; and connecting a MOS device of an n-th layer of the n layers with the MOS device of the (n+1)-th layer via metallic interconnection.

公开(公告)号：US10700124B1

公开(公告)日：2020-06-30

申请号：US16411431

申请日：2019-05-14

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Meiyin Yang ,  Jun Luo ,  Tengzhi Yang ,  Jing Xu

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A spin-orbit torque magnetoresistive random access memory, and a method for manufacturing a spin-orbit torque magnetoresistive random access memory are provided. The spin-orbit torque magnetoresistive random access memory includes a spin-orbit coupling layer and a magnetoresistive tunnel junction located on the spin-orbit coupling layer. The magnetoresistive tunnel junction includes a first magnetic layer, a tunneling layer, and a second magnetic layer that are sequentially stacked from bottom to top, and each of the first magnetic layer and the second magnetic layer has perpendicular anisotropy. In a direction of a current in the spin-orbit coupling layer, defects are generated in a part of the magnetoresistive tunnel junction by an ion implantation process.

公开(公告)号：US10600696B2

公开(公告)日：2020-03-24

申请号：US16421009

申请日：2019-05-23

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Zhengyong Zhu

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/3065 ,  B82Y10/00 ,  H01L29/267 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L29/04 ,  H01L29/165 ,  H01L29/423 ,  H01L29/78 ,  H01L21/225 ,  H01L21/324 ,  H01L29/08 ,  H01L29/10 ,  H01L29/15 ,  H01L29/205 ,  H01L29/45 ,  H01L29/778 ,  H01L21/308 ,  H01L21/822 ,  H01L27/092 ,  H01L21/3105

Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.

公开(公告)号：US20200066984A1

公开(公告)日：2020-02-27

申请号：US16489266

申请日：2017-02-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qi LIU ,  Xiaolong ZHAO ,  Sen LIU ,  Ming LIU ,  Hangbing LV ,  Shibing LONG ,  Yan WANG ,  Facai WU

IPC: H01L45/00

Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.

公开(公告)号：US20200027879A1

公开(公告)日：2020-01-23

申请号：US16337878

申请日：2017-07-31

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device including a first source/drain region at a lower portion thereof, a second source/drain region at an upper portion thereof, a channel region between the first source/drain region and the second source/drain region and close to peripheral surfaces thereof, and a body region inside the channel region. The semiconductor device may further include a gate stack formed around a periphery of the channel region.

公开(公告)号：US10483279B2

公开(公告)日：2019-11-19

申请号：US15753376

申请日：2015-11-23

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Tianchun Ye

IPC: H01L21/02 ,  H01L27/11582 ,  H01L21/306 ,  H01L21/324 ,  H01L21/28 ,  H01L29/792

Abstract: A method of manufacturing a semiconductor device, comprising the steps of: forming a gate dielectric layer and a first amorphous channel layer on a substrate; thinning the first amorphous channel layer; etching the first amorphous channel layer and the gate dielectric layer until the substrate is exposed; forming a second amorphous channel layer on the first amorphous channel layer and the substrate; annealing such that the first amorphous channel layer and the second amorphous channel layer are converted into a polycrystalline channel layer; and thinning the polycrystalline channel layer. According to the method of manufacturing semiconductor device of the present invention, the grain size of the polycrystalline thin film is increased by depositing a thick amorphous film and then annealing and thinning it. An additional protective layer is used to avoid etching damage on the sidewalls, effectively reducing the interface state and damage defects of the polycrystalline channel layer, thereby enhancing the reliability of the device.