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公开(公告)号:DE102011053641A1
公开(公告)日:2013-03-21
申请号:DE102011053641
申请日:2011-09-15
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SCHULZE HANS-JOACHIM , MAUDER ANTON , RUPP ROLAND
IPC: H01L29/04 , H01L21/336 , H01L29/16 , H01L29/78
Abstract: Eine Halbleitervorrichtung (100) weist einen Halbleiterkörper (101) aus SiC sowie einen Feldeffektransistor auf. Der Feldeffektransistor weist eine im Halbleiterkörper (101) aus SiC ausgebildete Driftzone (102) sowie eine polykristalline Siliziumschicht (103) auf dem Halbleiterkörper (101) auf, wobei die polykristalline Siliziumschicht (103) eine mittlere Korngröße im Bereich von 10 nm bis 50 µm aufweist und ein Sourcegebiet (103s) sowie ein Bodygebiet (103b) umfasst. Darüber hinaus weist der Feldeffekttransistor eine an das Bodygebiet (103b) angrenzende Gatestruktur (104)auf.
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公开(公告)号:DE102005046710B4
公开(公告)日:2012-12-06
申请号:DE102005046710
申请日:2005-09-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor: MAUDER ANTON , KROENER FRIEDRICH DR
Abstract: Verfahren zur Herstellung einer Bauelementanordnung mit folgenden Schritten: a) Bereitstellen eines Halbleiterchips (10), b) Herstellen eines Trägers gemäß den Schritten c) bis f) durch c) Bereitstellen eines Gemenges, das ein Metall (3) sowie eine Vielzahl von Kohlefasern (2) umfasst, und d) Herstellen eines Sinterkörpers (4, 5) durch Versintern des Gemenges, e) Verringern der Oberflächenrauigkeit des Sinterkörpers (4, 5) durch Schleifen zumindest an einer zur Montage des Halbleiterchips (10) vorgesehenen Stelle, f) Aufbringen einer Metallisierungsschicht (4a, 5a) auf den Sinterkörper (4, 5), und g) Herstellen einer eutektischen Verbindung zwischen dem Halbleiterchip (10) und der Metallisierungsschicht (4a, 5a) des Trägers.
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公开(公告)号:DE102007017788A1
公开(公告)日:2008-10-30
申请号:DE102007017788
申请日:2007-04-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor: MAUDER ANTON , SCHULZE HOLGER , GUTT THOMAS
IPC: H01L21/22 , H01L21/265
Abstract: The method involves providing a semiconductor body (1). A dopant (2) is introduced into the semiconductor body, where the dopant is sulphur, selenium, Indium or antimony. A short-time heat treatment is executed at a temperature. Another heat treatment which is longer that the former heat treatment is executed at another temperature for forming a doping zone, where the former temperature is higher than the latter temperature. The former heat treatment is executed in such a manner that no diffusion of the dopant takes place in the semiconductor body.
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公开(公告)号:DE10240107B4
公开(公告)日:2008-03-06
申请号:DE10240107
申请日:2002-08-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor: MAUDER ANTON , SCHULZE HANS-JOACHIM , NIEDERNOSTHEIDE FRANZ-JOSEF , FALCK ELMAR
IPC: H01L29/06 , H01L21/328 , H01L29/739 , H01L29/745 , H01L29/861 , H01L29/87
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公开(公告)号:DE10357796B4
公开(公告)日:2007-09-27
申请号:DE10357796
申请日:2003-12-10
Applicant: INFINEON TECHNOLOGIES AG
Inventor: MAUDER ANTON , WERNER WOLFGANG
IPC: H01L29/861 , H01L21/328 , H01L29/167 , H01L29/70 , H01L29/739 , H01L29/74 , H01L29/872
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公开(公告)号:DE10238797B4
公开(公告)日:2007-09-20
申请号:DE10238797
申请日:2002-08-23
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SCHULZE HANS-JOACHIM , MAUDER ANTON , FALCK ELMAR
IPC: H01L29/861 , H01L21/329 , H01L29/06
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公开(公告)号:DE102005011652B4
公开(公告)日:2007-06-14
申请号:DE102005011652
申请日:2005-03-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor: MAUDER ANTON , ACHATZ GERFRIED
Abstract: The production of a semiconductor component comprises arranging one or more semiconductor chips (1, 2) on a substrate (3) and applying a mask-forming/masking layer (8) is to the surface of the substrate, where before applying the masking layer the actual positions of the contact surfaces are determined. Through-apertures are made in the masking-layer at the regions located over the identified contact surfaces (18,19). Subsequently, on the masking layer at least one conductor layer is applied and penetrates through the apertures to the contact surfaces.
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78.
公开(公告)号:DE102005046710A1
公开(公告)日:2007-04-05
申请号:DE102005046710
申请日:2005-09-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor: MAUDER ANTON , KROENER FRIEDRICH
Abstract: Carrier comprises a sintered body (4, 5) made from carbon fibers and a metal (3). Independent claims are also included for: (a) method for producing a carrier; and (b) component arrangement comprising the above carrier.
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公开(公告)号:DE102005039804A1
公开(公告)日:2007-03-15
申请号:DE102005039804
申请日:2005-08-22
Applicant: INFINEON TECHNOLOGIES AG
Inventor: MAUDER ANTON , SCHULZE HANS-JOACHIM , STRACK HELMUT , PFIRSCH FRANK
IPC: H01L29/78
Abstract: Drift path (5) or drift zone, extends laterally in a semiconductor body (7) between first and second electrodes (8, 9). Its material is type n. It is arranged on an insulating- or complementary, p type semiconductor substrate (10). On the top of the drift path (11), above the semiconductor body, the potential distribution structure (6) is arranged between first and second electrodes. The potential distribution structure divides the potential between these electrode in stages, producing a correspondingly-stepped field profile in the drift path below it. Insulation layer (13) intervenes between the underside (12) of the potential distribution structure and the top of the drift path. This (13) is SiO 2, Al 2O 3, or TiO 2. It is alternatively a silicon dioxide- or silicon nitride film. The potential distribution structure includes a layered capacitance between the electrodes on top of the drift path. This includes alternating conductive plates (15) and insulating plates (16). The surface normal (F) to these plates, is parallel to the drift path. Mean spacing between the conductive plates varies. Lateral capacity of the layered capacitance exceeds that of the drift path. In a variant design, a diode stack replaces the layered capacitance. Further variants based on the foregoing principles are described. Doping concentration in the drift path lies between 1 x 10 16> cm -3> and 2 x 10 17> cm -3>. The semiconductor component (1) is a lateral MOSFET, lateral JFET, lateral IGFET, PIN diode or Schottky diode. It has a planar gate structure or trench gate structure. The trench structure of the gate electrode (G) passes through a body zone (35). An independent claim IS INCLUDED FOR the corresponding method of manufacture.
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公开(公告)号:DE102005026408B3
公开(公告)日:2007-02-01
申请号:DE102005026408
申请日:2005-06-08
Applicant: INFINEON TECHNOLOGIES AG
IPC: H01L21/328 , H01L21/265 , H01L21/324 , H01L29/739 , H01L29/74 , H01L29/861
Abstract: A method for producing a buried stop zone in a semiconductor body and a semiconductor component having a stop zone, the method including providing a semiconductor body having a first and a second side and a basic doping of a first conduction type. The method further includes irradiating the semiconductor body via one of the sides with protons, as a result of which protons are introduced into a first region of the semiconductor body situated at a distance from the irradiation side. The method also includes carrying out a thermal process in which the semiconductor body is heated to a predetermined temperature for a predetermined time duration, the temperature and the duration being chosen such that hydrogen-induced donors are generated both in the first region and in a second region adjacent to the first region in the direction of the irradiation side.
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