Abstract:
A compensating component and a method for the production thereof are described. Compensating regions are produced by implanting sulfur or selenium in a p-conductive semiconductor layer or, are provided as p-conductive regions, which are doped with indium, thallium and/or palladium, in a cluster-like manner inside an n-conductive region.
Abstract:
The invention relates to a method for producing a body area for a vertical MOS transistor array in a semiconductor body, wherein the body area has at least one channel region disposed between the source area and the drain area and borders on a gate electrode. A first implantation of doping material is effected in the semiconductor body, wherein the maximum of doping material of the first implantation is placed in the back part of the channel region (11) within the semiconductor body. At least a second implantation of doping material is then effected with a smaller dose than in the first implantation, wherein the maximum of doping material of the second implantation lies within the semiconductor body below the maximum of doping material of the first implantation. Subsequently, the doping material is diffused off.
Abstract:
Verfahren zum Herstellen eines Halbleiterbauelements, mit den folgenden Schritten:Platzieren von mindestens zwei Halbleiterchips (3) auf einem Träger (1);Überdecken der mindestens zwei Halbleiterchips (3) mit einem Vergussmaterial (7), um einen vergossenen Körper (70) zu bilden;Dünnen des vergossenen Körpers (70), wodurch eine erste Hauptoberfläche der mindestens zwei Halbleiterchips (3) freigelegt wird;Ausbilden je einer Kontaktstelle (9) auf der freigelegten Hauptoberfläche der mindestens zwei Halbleiterchips (3) nach dem Dünnen;Aufbringen einer ersten Schicht (13, 19) aus leitfähigem Material über der ersten Hauptoberfläche der mindestens zwei Halbleiterchips (3) nach dem Ausbilden je einer Kontaktstelle (9), wobei die erste Schicht (13, 19) aus leitfähigem Material elektrisch mit der Kontaktstelle (9) an jedem der mindestens zwei Halbleiterchips (3) verbunden ist;Entfernen des Trägers (1) von den mindestens zwei Halbleiterchips (3); undZertrennen des vergossenen Körpers (70) derart, dass die mindestens zwei Halbleiterchips (3) vereinzelt werden, wobei die Halbleiterchips (3) Leistungshalbleiterchips sind.
Abstract:
Drift path (5) or drift zone, extends laterally in a semiconductor body (7) between first and second electrodes (8, 9). Its material is type n. It is arranged on an insulating- or complementary, p type semiconductor substrate (10). On the top of the drift path (11), above the semiconductor body, the potential distribution structure (6) is arranged between first and second electrodes. The potential distribution structure divides the potential between these electrode in stages, producing a correspondingly-stepped field profile in the drift path below it. Insulation layer (13) intervenes between the underside (12) of the potential distribution structure and the top of the drift path. This (13) is SiO 2, Al 2O 3, or TiO 2. It is alternatively a silicon dioxide- or silicon nitride film. The potential distribution structure includes a layered capacitance between the electrodes on top of the drift path. This includes alternating conductive plates (15) and insulating plates (16). The surface normal (F) to these plates, is parallel to the drift path. Mean spacing between the conductive plates varies. Lateral capacity of the layered capacitance exceeds that of the drift path. In a variant design, a diode stack replaces the layered capacitance. Further variants based on the foregoing principles are described. Doping concentration in the drift path lies between 1 x 10 16> cm -3> and 2 x 10 17> cm -3>. The semiconductor component (1) is a lateral MOSFET, lateral JFET, lateral IGFET, PIN diode or Schottky diode. It has a planar gate structure or trench gate structure. The trench structure of the gate electrode (G) passes through a body zone (35). An independent claim IS INCLUDED FOR the corresponding method of manufacture.
Abstract:
The method involves producing space agglomerates within a semiconductor body (2) e.g. silicon wafer, of a power transistor, while the wafer is irradiated with silicon ions or helium ions. Diffusion processes are accomplished in order to store heavy metal e.g. gold, in the agglomerate. The zone of increased ion recombination is produced in a body zone of the power transistor.
Abstract:
A doped semiconductor zone is formed in semiconductor body (100) by introducing dopant particles to side of semiconductor body; irradiating semiconductor body via the one side with further particles in region containing the dopant particles; and carrying out thermal treatment by ways of which the semiconductor body is heated, in the region containing the dopant particles, to less than 700[deg]C to activate the implanted dopant particles.
Abstract:
Metal-semiconductor contact comprises a metallizing layer (3) forming an ohmic metal-semiconductor contact arranged on a doped semiconductor layer (1). A first doping material is provided for doping of the semiconductor layer so that the electrically active doping concentration in the semiconductor layer is a fraction of the doping concentration in the semiconductor layer. Independent claims are also included for the following: (1) Semiconductor component arranged in a semiconductor body; (2) Integrated circuit containing the semiconductor component; and (3) Process for the production of the metal-semiconductor contact.