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    72.
    发明专利
    未知

    公开(公告)号：DE602006012011D1

    公开(公告)日：2010-03-18

    申请号：DE602006012011

    申请日：2006-03-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

    IPC: H03K17/10 ,  G11C16/12 ,  H01L27/02

    Abstract: A circuit is disclosed. The circuit comprises a first input terminal (INA1), a second input terminal (INA2) and an output terminal (OUT). The circuit further includes a first circuital branch (610) connected between the first input terminal and the output terminal, and a second circuital branch (620) connected between the second input terminal and the output terminal. The first circuital branch is selectively activatable for coupling the first input terminal with the output terminal, and the second circuital branch is selectively activatable for coupling the second input terminal with the output terminal. The first and second circuital branches comprise each at least one electronic device having at least a first and a second device terminals. Said at least one electronic device is designed to guarantee the capability of sustaining voltage differences across at least the first and second device terminals thereof that are up-limited in absolute value by a first predetermined maximum value lower than the maximum of absolute values of voltage differences between the output terminal and the first input terminal, and between the output terminal and the second input terminal, respectively.

    74.
    发明专利
    未知

    公开(公告)号：DE60327032D1

    公开(公告)日：2009-05-20

    申请号：DE60327032

    申请日：2003-10-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

    IPC: G11C11/00

    Abstract: A semiconductor memory comprises a plurality of memory cells (MC), for example Flash memory cells, arranged in a plurality of lines (LBL), and a plurality of memory cell access signal lines (MBL), each one associated with at least one respective line of memory cells, for accessing the memory cells of the at least one respective line of memory cells; each signal line has a capacitance (CMBL) intrinsically associated therewith. A plurality of volatile memory cells is provided, each having a capacitive storage element. Each volatile memory cell is associated with a respective signal line, and the respective capacitive storage element formed by the capacitance intrinsically associated with the respective signal lines. In particular, the parasitic capacitances associated with bit lines of a matrix of memory cells can be exploited as capacitive storage elements.

    75.
    发明专利
    未知

    公开(公告)号：DE60129786T2

    公开(公告)日：2008-04-30

    申请号：DE60129786

    申请日：2001-01-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

    IPC: G11C11/56 ,  G11C7/06 ,  G11C16/06 ,  G11C16/02 ,  G11C16/26

    Abstract: The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell (36) by a capacitive element (22, 23). The capacitive element (22, 23) is initially charged and then discharged linearly in a preset time, while the memory cell (36) is biased at a constant voltage. In a first operating mode, initially a first capacitor (22) and a second capacitor (23) are respectively charged to a first charge value and to a second charge value. The second capacitor (23) is discharged through the memory cell (36) at a constant current in a preset time; the first charge is shared between the first capacitor (22) and the second capacitor (23); and then the shared charge is measured.

    76.
    发明专利
    未知

    公开(公告)号：DE69930238D1

    公开(公告)日：2006-05-04

    申请号：DE69930238

    申请日：1999-06-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  OHBA ,  CARRERA MARCELLO

    IPC: G11C16/06 ,  G11C16/12 ,  G11C8/00 ,  G11C8/08 ,  G11C11/56 ,  H03K19/173

    Abstract: The row decoder includes, for each word line (WL) of the memory (2), a respective biasing circuit (54) receiving at the input a row selection signal (SR ) switching, in preset operating conditions, between a supply voltage (VCC) and a ground voltage (VGND) and supplying at the output a biasing signal (R ) for the respective word line (WL) switching between a first operating voltage (VPC), in turn switching at least between the supply voltage (VCC) and a programming voltage (VPP) higher than the supply voltage (VCC), and a second operating voltage (VNEG), in turn switching at least between the ground voltage (VGND) and an erase voltage (VERN) lower than the ground voltage (VGND). Each biasing circuit (54) includes a level translator circuit (58) receiving at the input the row selection signal (SR ) and supplying as output a control signal (CM ) switching between the first and the second operating voltages (VPC, VNEG) and an output driver circuit (60) receiving as input the control signal (CM ) and supplying at the output the biasing signal (R ).

    77.
    发明专利
    未知

    公开(公告)号：DE69831728D1

    公开(公告)日：2006-02-09

    申请号：DE69831728

    申请日：1998-04-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  ZANARDI STEFANO ,  BRANCHETTI MAURIZIO ,  GHEZZI STEFANO

    IPC: G05F3/20 ,  H01L27/115

    Abstract: The invention relates to an integrated structure (1) for memory cells formed over a semiconductor substrate (2) doped with a first dopant type and including at least one memory cell (CM) in turn formed in a conductive well (3) provided in said semiconductor substrate (2) and doped with a second dopant type, said conductive well (3) having an additional well (4) formed therein which is doped with the first dopant type and comprises active areas (5,6) of the memory cell (CM). According to the invention, a substrate bias terminal (8), formed in the additional well (4), is further associated with the memory cell (CM) to receive a suitable bias voltage (Vpol) to lower the threshold voltage (Vth) of the memory cell (CM) by body effect. The invention also relates to a biasing device (13) for a memory cell (CM) which has at least one substrate bias terminal (8) associated therewith, the biasing device comprising at least a first sub-threshold circuitry block (A) adapted to supply an appropriate current during the device standby phase through a restore transistor (M1) connected between a supply voltage reference (Vcc) and the substrate bias terminal (8) of the memory cell (CM), and having a control terminal connected to a bias circuit (14), in turn connected between the supply voltage reference (Vcc) and a ground voltage reference (GND) to drive the restore transistor (M1) with a current of limited value. The device according to the invention further comprises a second feedback block (B) for fast charging the substrate bias terminal (8), being connected between the supply voltage reference (Vcc) and the ground voltage reference (GND) and comprising a first bias transistor (M2) having a control terminal connected to the ground voltage reference (GND) via a stabilization transistor (M3), having in turn a control terminal connected to an output node (OC), and to the control terminal of a first regulation transistor (M4) connected between the supply voltage reference (Vcc) and the ground voltage reference (GND), the stabilization transistor (M3) and first regulation transistor (M4) providing feedback for the bias transistor (M2), thereby to restrict the voltage range of the output node (OC).

    80.
    发明专利
    未知

    公开(公告)号：DE60015916D1

    公开(公告)日：2004-12-23

    申请号：DE60015916

    申请日：2000-02-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GHEZZI STEFANO ,  FERRARIO DONATO ,  YERO EMILIO ,  CAMPARDO GIOVANNI

    IPC: H03K19/177

    Abstract: A programmable logic array (PLA) has at least an AND plane comprising an array of transistors arranged in rows and columns, the transistors belonging to a same column being connected in series with each other, the two end current terminals of said series of transistors being coupled to the supply voltage rail (VDD) and to a reference (GND), respectively, the transistors of the first row and of the last row of the array having their control terminals coupled to respective opposite enabling/disabling potentials. To each row of said array, with the exception of the first and the last row, are associated three control lines, the first line being coupled to a first input value, the second line being coupled to the inverted logic value of the first input value and the third line being coupled to a voltage sufficient to keep in a state of conduction the transistors of the row connected to it. Each transistor of each row except the first and the last row has its control terminal connected to one of the three control lines associated to the row. An OR plane comprises at least an array of transistors arranged in rows and columns, the transistors belonging to a same column having their respective control terminals connected to a control line and a first current terminal coupled to a reference potential (GND), each transistor of each row of the array having a second current terminal connected or not to a respective output line. The second current terminal of each transistor of the array that is not connected to a respective output line is short-circuited to the first current terminal of the same transistor.

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