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    71.
    发明专利
    未知

    公开(公告)号：DE69921974D1

    公开(公告)日：2004-12-23

    申请号：DE69921974

    申请日：1999-06-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  ZAMMATTIO MATTEO ,  CAMPARDO GIOVANNI

    IPC: G11C16/06 ,  G11C8/12 ,  G11C16/12 ,  G11C16/16 ,  G11C16/08

    Abstract: The memory device (21) has hierarchical sector decoding (24, 25). A plurality of groups of supply lines (28-32) is provided, one for each sector row, extending parallel to the sector rows. A plurality of switching stages (35) are each connected between a respective sector (15) and a respective group of supply lines (28-32); the switching stages (35) connected to sectors (15) arranged on a same column are controlled by same control signals (S0, S1) supplied on control lines (40) extending parallel to the columns of sectors. For biasing the sectors, modification voltages (NW, SB, VNEG) are sent to at least one selected group of biasing lines (28-32), and control signals (SO, S1) are sent to the switching stages connected to a selected sector column.

    72.
    发明专利
    未知

    公开(公告)号：DE69916783D1

    公开(公告)日：2004-06-03

    申请号：DE69916783

    申请日：1999-02-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI

    IPC: G11C16/02 ,  G11C11/56

    Abstract: The sensing circuits (30, 31, 32) comparing the current flowing in the cell with a plurality of reference currents are not identical to each other but differently amplify the compared currents. In particular, the sensing circuit (32) associated with the lowest reference current (IR3) amplifies (33b) the cell current more than the other sensing circuits (30, 31) and to the respective reference current (33c). The current dynamics is thereby increased and it is possible to keep the reading voltage low, since the inherent characteristic of the lowest reference current (IR3) may be very close to or directly superimposed on that of the immediately preceding memory cell current distribution (IM3), retaining the possibility of discriminating between the different logic levels.

    73.
    发明专利
    未知

    公开(公告)号：DE69727937D1

    公开(公告)日：2004-04-08

    申请号：DE69727937

    申请日：1997-11-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  ZAMMATTIO MATTEO ,  FERRARIO DONATO

    IPC: G11C11/41 ,  G11C8/18 ,  G11C8/00 ,  G11C7/00

    Abstract: The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.

    76.
    发明专利
    未知

    公开(公告)号：DE69909969D1

    公开(公告)日：2003-09-04

    申请号：DE69909969

    申请日：1999-05-12

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MANSTRETTA ALESSANDRO ,  MICHELONI RINO

    IPC: G06F12/16 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

    Abstract: Non-volatile memory device organised with memory cells that are arranged by row and by column, comprising at least a sector of matrix cells (100), row decoders (D) and column decoders suitable to decode address signals and to activate respectively said rows or said columns, at least a sector of redundancy cells (110) such that it is possible to substitute a row of said sector of matrix cells with a row of said sector of redundancy cells. Said non-volatile memory device comprises a local column decoder (L) for said matrix sector (100) and a local column decoder (L) for said redundancy sector (110). The local column decoders (L) are controlled by external signals so that said row of said redundancy sector (110) is activated simultaneously with said row of said matrix sector (100).

    77.
    发明专利
    未知

    公开(公告)号：IT1314178B1

    公开(公告)日：2002-12-04

    申请号：ITTO990798

    申请日：1999-09-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  SACCO ANDREA ,  SCOTTI MARCO

    IPC: H03K19/003

    Abstract: A circuit for biasing the bulk terminal of a first MOS transistor having a first terminal connected to a first line set to a first potential, and a second terminal connected to a second line set to a second potential. The biasing circuit includes a second and a third MOS transistors having first terminals connected respectively to the first line and to the second line, second terminals connected to the bulk terminal of the first MOS transistor, and control terminals connected respectively to the second and to the first line.

    80.
    发明专利
    未知

    公开(公告)号：ITMI20002367A1

    公开(公告)日：2002-05-01

    申请号：ITMI20002367

    申请日：2000-10-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  SACCO ANDREA

    IPC: G11C16/10 ,  G11C16/24

    Abstract: A pulse programming method for a non-volatile memory device includes: addressing memory cells to be programmed within the device by selecting corresponding hierarchic decoder transistors; biasing the gate terminals of the memory cells; and programming the memory cells by applying a voltage pulse, regulated by a bias circuit, to the drain terminals of the memory cells. Advantageously, the programming method further comprises a step of precharging an internal node of the bias circuit before starting the programming step, the internal node being connected to a parasitic capacitance of the memory device.

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