公开(公告)号：US11991825B2

公开(公告)日：2024-05-21

申请号：US16392112

申请日：2019-04-23

Applicant: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yuanda Lu ,  Junjie Ma ,  Shipeng Wang ,  Ming Zhai ,  Jian Sang ,  Haiwei Sun ,  Dongjia Hao

IPC: F21V8/00 ,  H01R12/65 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/118 ,  H01R12/65 ,  H05K1/028 ,  H05K1/111 ,  H05K2201/09372 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/09781 ,  H05K2201/10378

Abstract: The present disclosure provides a flexible circuit board, a light bar, a light source and a display device. The light source includes a flexible circuit board having at least one effective welding portion and a light bar having at least one effective pad, the at least one effective welding portion being in one-to-one correspondence with the at least one effective pad, and the effective welding portion being fixed to a corresponding effective pad to transmit a signal loaded by itself to the corresponding effective pad. The flexible circuit board further includes at least one auxiliary welding portion, the light bar further includes at least one auxiliary pad that is in one-to-one correspondence with the at least one auxiliary welding portion, and the auxiliary welding portion is fixed to a corresponding auxiliary pad to enhance the firm fixing between the flexible circuit board and the light bar.

公开(公告)号：US20240006295A1

公开(公告)日：2024-01-04

申请号：US18466610

申请日：2023-09-13

Applicant: InnoLux Corporation

Inventor： Chung-Chun CHENG ,  Kuang-Ming FAN ,  Yao-Wen HSU

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H05K1/11

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L24/20 ,  H01L24/19 ,  H05K1/11 ,  H05K1/0268 ,  H01L2224/214 ,  H01L23/49822 ,  H01L2224/19 ,  H05K2201/09372 ,  H05K1/111

Abstract: A manufacturing method of electronic components includes the steps of: providing an insulating layer including a first region and a second region; providing a first metal layer disposed in the first region of the insulating layer; providing a second metal layer disposed on the first metal layer; providing a metal line in the second region of the insulating layer, wherein the metal line is electrically connected to the first metal layer; and removing the metal line to form an electronic component, wherein the electronic component includes the insulating layer; and a first metal bump disposed on the insulating layer and including: the first metal layer disposed on the insulating layer; and the second metal layer disposed on the first metal layer.

公开(公告)号：US11798875B2

公开(公告)日：2023-10-24

申请号：US17535167

申请日：2021-11-24

Applicant: InnoLux Corporation

Inventor： Chung-Chun Cheng ,  Kuang-Ming Fan ,  Yao-Wen Hsu

IPC: H05K1/11 ,  H05K1/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L24/19 ,  H01L24/20 ,  H05K1/11 ,  H05K1/111 ,  H01L23/49822 ,  H01L2224/19 ,  H01L2224/214 ,  H05K1/0268 ,  H05K2201/0338 ,  H05K2201/0347 ,  H05K2201/09372

Abstract: An electronic component includes: an insulating layer; and a first metal bump disposed on the insulating layer and provided with: a first metal layer disposed on the insulating layer; and a second metal layer disposed on the first metal layer, wherein, in a cross-sectional view of the electronic component, the first metal layer has a first width, the second metal layer has a second width, and the first width is smaller than the second width.

公开(公告)号：US09856140B2

公开(公告)日：2018-01-02

申请号：US14512105

申请日：2014-10-10

Applicant: OCE-TECHNOLOGIES B.V.

Inventor： Maikel A. J. Huygens ,  René J. Van Der Meer ,  Reinier Pannekoek ,  Alex N. Westland

IPC: G01R31/02 ,  B81C99/00 ,  B81B7/00 ,  B81C1/00 ,  G01R31/26 ,  H05K1/11 ,  B41J2/14 ,  B41J2/16 ,  H05K1/02

CPC classification number: B81C99/004 ,  B41J2/14233 ,  B41J2/161 ,  B41J2/1632 ,  B41J2/1635 ,  B41J2002/14241 ,  B41J2002/14459 ,  B41J2002/14491 ,  B81B7/007 ,  B81B2201/052 ,  B81B2207/03 ,  B81C1/00301 ,  G01R31/02 ,  G01R31/2601 ,  H05K1/0268 ,  H05K1/111 ,  H05K2201/09372

Abstract: A substrate plate is provided for at least one MEMS device to be mounted thereon. The MEMS device has a certain footprint on the substrate plate, and the substrate plate has a pattern of electrically conductive leads to be connected to electric components of the MEMS device. The pattern forms contact pads within the footprint of the MEMS device and includes at least one lead structure that extends on the substrate plate outside of the footprint of the MEMS device and connects a number of the contact pads to an extra contact pad. The lead structure is a shunt bar that interconnects a plurality of contact pads of the MEMS device and is arranged to be removed by means of a dicing cut separating the substrate plate into a plurality of chip-sized units. At least a major part of the extra contact pad is formed within the footprint of one of the MEMS devices.

公开(公告)号：US20170318669A1

公开(公告)日：2017-11-02

申请号：US15649830

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Daniel Sobieski ,  Kyu Oh Lee ,  Sri Ranga Sai Boyapati

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/113 ,  H05K3/0041 ,  H05K3/181 ,  H05K3/188 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09218 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/096 ,  H05K2201/09654 ,  H05K2203/0548

Abstract: Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.

公开(公告)号：US20160324002A1

公开(公告)日：2016-11-03

申请号：US15105723

申请日：2014-10-14

Applicant: Auto-Kabel Management GmbH

Inventor： Wacim TAZARINE ,  Simon BETSCHER ,  Frank GRONWALD

IPC: H05K1/14 ,  H05K1/11 ,  H05K3/36 ,  H05K1/18

CPC classification number: H05K1/145 ,  C23C14/042 ,  H01L23/142 ,  H01L23/367 ,  H01L23/3677 ,  H01L2924/0002 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/056 ,  H05K1/111 ,  H05K1/117 ,  H05K1/142 ,  H05K1/181 ,  H05K1/182 ,  H05K3/28 ,  H05K3/282 ,  H05K3/368 ,  H05K2201/09372 ,  H05K2201/09554 ,  H05K2201/10166 ,  H05K2201/10689 ,  H05K2203/1377 ,  H01L2924/00

Abstract: Circuit having a first printed circuit board and a second printed circuit board. In the circuit, the printed circuit boards spaced apart from one another by means of an air gap are mechanically connected together by at least one power semiconductor.

Abstract translation: 具有第一印刷电路板和第二印刷电路板的电路。 在电路中，通过气隙彼此间隔开的印刷电路板通过至少一个功率半导体机械连接在一起。

公开(公告)号：US08887385B2

公开(公告)日：2014-11-18

申请号：US13534217

申请日：2012-06-27

Applicant: Kai-Wen Wu

Inventor： Kai-Wen Wu

IPC: H05K3/02

CPC classification number: H05K1/0253 ,  H01R12/53 ,  H01R13/6474 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/111 ,  H05K1/117 ,  H05K3/40 ,  H05K2201/09372 ,  H05K2201/10287 ,  Y10T29/49004 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A circuit board assembly includes a circuit board, at least one pad formed on the circuit board, and at least one connection line. Each of the at least one connection line includes a connection end connected to a respective one of the at least one pad and has the same resistance value as the respective pad.

Abstract translation: 电路板组件包括电路板，形成在电路板上的至少一个焊盘和至少一个连接线。 所述至少一个连接线中的每一个包括连接到所述至少一个焊盘中的相应一个焊盘并且具有与相应焊盘相同的电阻值的连接端。

公开(公告)号：US20140326495A1

公开(公告)日：2014-11-06

申请号：US14240960

申请日：2012-08-27

Applicant: Jose Ricardo Paniagua

Inventor： Jose Ricardo Paniagua

IPC: H05K1/11 ,  H05K3/42 ,  H05K3/10 ,  H05K3/00

CPC classification number: H05K1/116 ,  G06F17/5081 ,  G06F2217/82 ,  H05K1/0225 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/0005 ,  H05K3/0047 ,  H05K3/10 ,  H05K3/42 ,  H05K2201/0784 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/09718 ,  H05K2201/09727 ,  H05K2203/0207 ,  H05K2203/0242 ,  Y10T29/49165

Abstract: A printed circuit board for carrying high frequency signals. Conducting structures of the printed circuit board are shaped within breakout regions to limit impedance discontinuities in the signal paths between vias and conductive traces within the printed circuit board. Values of parameters of traces or anti-pads, for example, may be adjusted to provide a desired impedance. The specific values selected as part of designing a printed circuit board may match the impedance of the breakout region to that of the via. The parameters for which values are selected may include the trace width, thickness, spacing, length over an anti-pad or angle of exit from the breakout region.

Abstract translation: 用于承载高频信号的印刷电路板。 印刷电路板的导电结构在突出区域内成形，以限制印刷电路板内的通孔和导电迹线之间的信号路径中的阻抗不连续性。 痕迹或抗焊盘参数的值可以被调整以提供所需的阻抗。 选择作为设计印刷电路板的一部分的具体值可以将突破区域的阻抗与通孔的阻抗匹配。 选择值的参数可以包括迹线宽度，厚度，间隔，防焊盘上的长度或从断裂区域的出口角度。

公开(公告)号：US12127341B2

公开(公告)日：2024-10-22

申请号：US17875683

申请日：2022-07-28

Applicant: THALES

Inventor： Geoffroy Aupee ,  Pierre-Yves Michaud

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H05K1/181 ,  H05K3/10 ,  H05K3/42 ,  H05K3/4697 ,  H05K3/0094 ,  H05K3/04 ,  H05K2201/09372

Abstract: Embodiments provide a multilayer printed circuit board intended to connect electronic components, the board comprising a stack of a plurality of conductive layers, the conductive layers comprising two surface layers and one or more internal layers, the board comprising one or more counterbored holes, each counterbored hole comprising a portion with metallization opening onto one of the two surface layers and a portion without metallization opening onto the other surface layer; the multilayer printed circuit board may advantageously comprise one or more metal pads, each metal pad being joined to one of the two surface layers so as to occult the portion without metallization of a corresponding counterbored hole.

公开(公告)号：US12082346B2

公开(公告)日：2024-09-03

申请号：US18175898

申请日：2023-02-28

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Masahiro Kyozuka

IPC: H05K1/02 ,  H05K1/05 ,  H05K3/00

CPC classification number: H05K3/0011 ,  H05K1/0271 ,  H05K1/05 ,  H05K2201/093 ,  H05K2201/09372 ,  H05K2201/10204

Abstract: A wiring board includes a first insulating layer, a pad formed on one surface of the first insulating layer, a second insulating layer, formed on the one surface of the first insulating layer, and including an opening exposing the pad, and a reinforcing metal layer formed in contact with the first insulating layer, and provided around the pad so as to be separated from the pad in a plan view. The pad is disposed inside the opening without making contact with the second insulating layer. An end, on a side of the first insulating layer, in a portion of an inner side surface of the opening of the second insulating layer makes contact with the reinforcing metal layer, and an end in another portion of the inner side surface of the opening of the second insulating layer makes contact with the one surface of the first insulating layer.