公开(公告)号：KR1020020065261A

公开(公告)日：2002-08-13

申请号：KR1020010005690

申请日：2001-02-06

Applicant: 전자부품연구원

Inventor： 박종철 ,  강남기 ,  조현민 ,  임욱 ,  이재영

IPC: H05K3/40

CPC classification number: H05K3/4629 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/429

Abstract: PURPOSE: A ceramic layered part and a manufacturing method thereof are provided to simplify manufacture process and improve reliability of side terminals of the ceramic layered part. CONSTITUTION: A ceramic layered part comprises ceramic tapes(20), circuit patterns(23) and many plugs(22,26). The ceramic tapes(20) include via holes for connecting the circuit patterns(23) and via holes for side terminals. The plugs(22,26) are formed by filling the via holes with conductive paste. The viscosity of the conductive paste is more than 100,000 cps. The circuit patterns(23) are printed on the ceramic tapes(20). The circuit patterns(23) are overlapped with the plugs(26) for ensuring their connectivity. The ceramic tapes(20) having the plugs(22,26) and the circuit patterns(23) are layered so as to accurate align the plugs(22,26) and the circuit patterns(23) between the ceramic tapes(20). The layered ceramic tapes(20) are cut as dividing the plug(26) into two parts.

Abstract translation: 目的：提供一种陶瓷分层部件及其制造方法，以简化制造工艺，提高陶瓷层叠部件的侧端子的可靠性。 构成：陶瓷分层部分包括陶瓷带（20），电路图案（23）和许多插头（22,26）。 陶瓷带（20）包括用于连接电路图案（23）的通孔和用于侧端子的通孔。 通过用导电浆填充通孔来形成插头（22,26）。 导电糊的粘度大于100,000cps。 电路图案（23）印刷在陶瓷带（20）上。 电路图案（23）与插头（26）重叠以确保它们的连接。 具有插头（22,26）和电路图案（23）的陶瓷带（20）被层叠以便精确地对准陶瓷带（20）之间的插头（22,26）和电路图案（23）。 切割分层陶瓷带（20），将塞子（26）分成两部分。

公开(公告)号：KR1020020063404A

公开(公告)日：2002-08-03

申请号：KR1020010004048

申请日：2001-01-29

Applicant: 전자부품연구원

Inventor： 이우성 ,  유찬세 ,  박종철 ,  강남기 ,  이영신 ,  곽승범

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H05K1/0237

Abstract: PURPOSE: An RF(Radio Frequency) element built-in substrate of MCM(Multi-Chip Module)-C is provided to reduce the number of fabrication processes of the MCM-C by fabricating the MCM-C with active elements and manual elements such as an FET, a transistor, and a diode. CONSTITUTION: A resistance(11) and a capacitor(15) are formed on a ceramic substrate including manual elements. A conductive line(30) is arranged in an inside of the ceramic substrate. Active elements such as a transistor(21) are formed on an upper portion of the ceramic substrate including manual elements. A capacitor and pad pattern(15a) is used as a pad of the active elements and a capacitor(15) mounted in the ceramic substrate. The capacitor and pad pattern(15a) is exposed on an upper surface of the capacitor(15). The transistor(21) is located on the capacitor and pad pattern(15a).

Abstract translation: 目的：提供MCM（多芯片模块）-C的内置RF（射频）元件，以通过用有源元件和手动元件制造MCM-C来减少MCM-C的制造工艺数量 作为FET，晶体管和二极管。 构成：在包括手动元件的陶瓷基板上形成电阻（11）和电容器（15）。 导电线（30）布置在陶瓷衬底的内部。 诸如晶体管（21）的有源元件形成在包括手动元件的陶瓷基板的上部。 电容器和焊盘图案（15a）用作有源元件的焊盘和安装在陶瓷衬底中的电容器（15）。 电容器和焊盘图案（15a）暴露在电容器（15）的上表面上。 晶体管（21）位于电容器和焊盘图案（15a）上。

公开(公告)号：KR1020010036982A

公开(公告)日：2001-05-07

申请号：KR1019990044238

申请日：1999-10-13

Applicant: 전자부품연구원

Inventor： 박종철 ,  강남기 ,  이우성 ,  임욱 ,  조현민 ,  곽승범 ,  류대원 ,  유찬세

IPC: H01G4/30

CPC classification number: H01G4/30 ,  H01G4/005

Abstract: PURPOSE: A high frequency condenser for ceramic laminated module is provided to improve the capacitance characteristics and the high frequency characteristics by minimizing the condenser area and by reducing the signal transmission distance by the via contact. CONSTITUTION: The high frequency condenser for ceramic laminated module has the via contacts(18) on the center of the electrode patterns(10a,10b,10c,10d) and omits the pad of the electrode patterns. The multiple electrode patterns are connected alternatively. The electrode pattern has the square shaped plane structure where the capacitance is charged on that area and two holes on the center position of each electrode pattern. One hole of each electrode pattern is alternatively connected to the holes of adjacent electrode patterns, and the other hole of each electrode pattern is connected to the insulator pattern. The insulator patterns(14a,14b,14c,14d) are laminated between electrode patterns. The via holes(16a,16b,16c,16d) are formed on each insulator pattern and on each electrode pattern. All via holes are filled by conductive material to form the via contact.

Abstract translation: 目的：提供陶瓷层叠模块的高频电容器，通过最小化电容器面积和通过通孔接点减小信号传输距离，提高电容特性和高频特性。 构成：用于陶瓷层叠模块的高频电容器在电极图案（10a，10b，10c，10d）的中心具有通孔触点（18），并省略电极图案的焊盘。 多个电极图案交替连接。 电极图案具有方形平面结构，其中电容在该区域上充电，并且在每个电极图案的中心位置具有两个孔。 每个电极图案的一个孔替代地连接到相邻电极图案的孔，并且每个电极图案的另一个孔连接到绝缘体图案。 绝缘体图案（14a，14b，14c，14d）层叠在电极图案之间。 通孔（16a，16b，16c，16d）形成在每个绝缘体图案上和每个电极图案上。 所有通孔由导电材料填充以形成通孔接触。

公开(公告)号：KR1020010026505A

公开(公告)日：2001-04-06

申请号：KR1019990037857

申请日：1999-09-07

Applicant: 전자부품연구원

Inventor： 박종철 ,  강남기 ,  이우성 ,  임욱 ,  조현민 ,  곽승범 ,  유찬세

IPC: H01G4/33

CPC classification number: H01G4/30 ,  H01G4/005

Abstract: PURPOSE: A high-frequency condenser for a ceramic layer module is provided to improve characteristics of a capacity and a high-frequency by maximizing an effective area of an electrode pattern and shortening a signal transmitting distance. CONSTITUTION: A high-frequency condenser for a ceramic layer module includes a plurality of electrode patterns(10a,10b,10c,10d) and insulation layers(12a,12b,12c). Each electrode pattern has an effective area(A) in which an electrostatic capacity is stored. Each electrode pattern has a concave recess at its side. The electrode patterns are layered such that the concave recesses are located alternately, i.e. zigzag. Insulation patterns(14a,14b,14c,14d) are provided in the respective concave recesses. The electrode patterns and insulation layers are layered alternately by one and one. Each electrode pattern is formed with a pair of via holes(16a,16b,16c,16d) at its both sides including the insulation pattern. The via holes are filled with a conductive material to form via contacts(18a,18b).

Abstract translation: 目的：提供一种用于陶瓷层模块的高频电容器，通过最大化电极图案的有效面积和缩短信号传输距离来提高容量和高频特性。 构成：用于陶瓷层模块的高频电容器包括多个电极图案（10a，10b，10c，10d）和绝缘层（12a，12b，12c）。 每个电极图案具有存储静电电容的有效面积（A）。 每个电极图案在其侧面具有凹形凹部。 电极图案被层叠成使得凹凹槽交替地位于Z字形。 绝缘图案（14a，14b，14c，14d）设置在相应的凹形凹部中。 电极图案和绝缘层交替地层叠一层。 每个电极图案在其包括绝缘图案的两侧形成有一对通孔（16a，16b，16c，16d）。 通孔填充有导电材料以形成通孔触点（18a，18b）。

公开(公告)号：KR1020010026504A

公开(公告)日：2001-04-06

申请号：KR1019990037856

申请日：1999-09-07

Applicant: 전자부품연구원

Inventor： 강남기 ,  김상철 ,  고현종 ,  임욱 ,  류대원 ,  유찬세

IPC: B41F17/00

Abstract: PURPOSE: A side printing jig for chip is provided to allow the chip insertion work to be easily performed and minimize damage to the chip component, while improving printing characteristics by preventing movement of a squeezer or a roller during printing operation. CONSTITUTION: A jig comprises a first plate(10) having a plurality of chip holes(12) with a size larger than the side surface of a chip and a plurality of coupling holes(14) formed at corners of the first plate; a second plate(20) having a plurality of chip holes(22) with a size larger than the side surface of the chip and which are formed in a position corresponding to the chip holes of the first plate, and a horizontal slot(24) formed at corners of the second plate so as to correspond to the coupling holes of the first plate; a third plate(30) having a plurality of chip holes(32) with a size larger than the side surface of the chip and which are formed in a position corresponding to the chip holes of the first plate, and a vertical slot(34) formed at corners of the third plate so as to correspond to the coupling holes of the first plate; and a coupling member(40) for coupling the coupling hole, horizontal slot and the vertical slot.

Abstract translation: 目的：提供一种用于芯片的侧面打印夹具，以便容易地执行芯片插入工作，并且最小化对芯片部件的损坏，同时通过在打印操作期间防止挤压机或滚筒的移动来改善打印特性。 构成：夹具包括具有大于芯片侧表面的尺寸的多个切屑孔（12）的第一板（10）和形成在第一板的角部处的多个联接孔（14）; 第二板（20）具有多个尺寸大于芯片的侧表面的切屑孔（22），并且形成在与第一板的切屑孔对应的位置，以及水平槽（24） 形成在第二板的角部，以对应于第一板的连接孔; 具有多个切屑孔（32）的第三板（30），其尺寸大于所述芯片的侧表面，并且形成在与所述第一板的所述切屑孔相对应的位置;以及垂直槽（34） 形成在第三板的角部，以对应于第一板的连接孔; 以及用于联接所述联接孔，水平槽和所述垂直槽的联接构件（40）。

公开(公告)号：KR1020000040049A

公开(公告)日：2000-07-05

申请号：KR1019980055594

申请日：1998-12-17

Applicant: 전자부품연구원

Inventor： 강남기 ,  김상철 ,  고현종 ,  박인식 ,  유찬세 ,  임욱

IPC: H01F17/00

CPC classification number: H01F27/2804

Abstract: PURPOSE: A chip inductor is provided to improve the inductance and reduce the manufacturing cost by forming coil patterns and repeatedly stacking the coil patterns. CONSTITUTION: A chip inductor comprises at least one first ceramic sheet(105,107,109,111), and a plurality of second ceramic sheets(103). A conductive pattern is formed in the first ceramic sheet(105,107,109,111). The conductive patterns of the first ceramic sheet(105,107,109,111) are electively connected to one another. The second ceramic sheets(103) are disposed above and under the first ceramic sheet(105,107,109,111). The second ceramic sheets(103) has electrode patterns which are electrically connected to the conductive patterns. A conductive pattern is wound on the first ceramic sheet(105,107,109,111) more than once.

Abstract translation: 目的：提供芯片电感器，通过形成线圈图案并重复堆叠线圈图案来提高电感并降低制造成本。 构成：芯片电感器包括至少一个第一陶瓷片（105,107,109,111）和多个第二陶瓷片（103）。 在第一陶瓷片（105,107,109,111）中形成导电图案。 第一陶瓷片（105,107,109,111）的导电图案彼此选择性连接。 第二陶瓷片（103）设置在第一陶瓷片（105,107,109,111）的上方和下方。 第二陶瓷片（103）具有电连接到导电图案的电极图案。 导电图案不止一次地卷绕在第一陶瓷片（105,107,109,111）上。

公开(公告)号：KR1020000040047A

公开(公告)日：2000-07-05

申请号：KR1019980055592

申请日：1998-12-17

Applicant: 전자부품연구원

Inventor： 강남기 ,  김상철 ,  고현종 ,  박인식 ,  유찬세 ,  임욱

IPC: H01F17/00

Abstract: PURPOSE: A chip inductor is provided to improve the productivity of the chip inductor by using a via hole. CONSTITUTION: A chip inductor comprises at least one first ceramic sheet(101,103,105), a second ceramic sheet(109), a third ceramic sheet(107), and a paste(117b). A conductive pattern is formed in the first ceramic sheet(101,103,105). The conductive pattern is electively connected top the conductive pattern of a ceramic sheet which is stacked. The second ceramic sheet(109) is stacked on the first ceramic sheet(101,103,105). The second ceramic sheet(109) is electrically connected to the conductive pattern. The third ceramic sheet(107) is stacked under the first ceramic sheet(101,103,105). The paste(117b) comprises a fourth ceramic sheet(111,113). The paste(117b) has a via hole(117c,117d).

Abstract translation: 目的：提供芯片电感，通过使用通孔提高芯片电感的生产率。 构成：芯片电感器包括至少一个第一陶瓷片（101,103,105），第二陶瓷片（109），第三陶瓷片（107）和糊（117b）。 在第一陶瓷片（101,103,105）中形成导电图案。 导电图案选择性地连接在堆叠的陶瓷片的导电图案上。 第二陶瓷片（109）堆叠在第一陶瓷片（101,103,105）上。 第二陶瓷片（109）电连接到导电图案。 第三陶瓷片（107）堆叠在第一陶瓷片（101,103,105）的下方。 浆料（117b）包括第四陶瓷片（111,113）。 糊（117b）具有通孔（117c，117d）。

公开(公告)号：KR1020000024888A

公开(公告)日：2000-05-06

申请号：KR1019980041680

申请日：1998-10-02

Applicant: 전자부품연구원

Inventor： 김상철 ,  강남기 ,  박인식 ,  고현종 ,  김종대

IPC: H01F17/00

CPC classification number: H01F17/0013 ,  H01F27/362

Abstract: PURPOSE: A stack-type chip inductor is provided to increase an inductance value without a marking. CONSTITUTION: In a stack-type chip inductor, a plurality of first ceramic sheets(110,120)have an electrode pattern(111,121) functioning as a coil and a via hole(112) filled by a conductive paste and connected to the electrode pattern, respectively. A second ceramic sheet(222) and a third ceramic sheet(232) are formed over and under the first ceramic sheets, respectively, and have an electrode pattern for an external connection, respectively. A fourth ceramic sheet(410) and a fifth ceramic sheet(420) are formed over and under the second and third ceramic sheets, respectively, and have first and second metal patterns for an electromagnetic wave shield, respectively.

Abstract translation: 目的：提供堆叠型片式电感器，以增加电感值而无需标记。 构成：在堆叠型片式电感器中，多个第一陶瓷片（110,120）具有用作线圈的电极图案（111,121）和由导电膏填充并分别连接到电极图案的通孔（112） 。 在第一陶瓷片上分别形成第二陶瓷片（222）和第三陶瓷片（232），并分别具有用于外部连接的电极图案。 分别在第二陶瓷片和第三陶瓷片上形成第四陶瓷片（410）和第五陶瓷片（420），并且分别具有用于电磁波屏蔽的第一和第二金属图案。

公开(公告)号：KR1020000013039A

公开(公告)日：2000-03-06

申请号：KR1019980031688

申请日：1998-08-04

Applicant: 전자부품연구원

Inventor： 강남기 ,  박인식 ,  임욱 ,  유찬세 ,  김종대 ,  고현종

IPC: H01F27/00

CPC classification number: H01F27/2804 ,  H01F17/0006

Abstract: PURPOSE: A stack type chip inductor is provided to diminish cost and the number of processes by diminishing the number of masks for forming a conductive pattern which is formed on a ceramic sheet of stack type chip inductor. CONSTITUTION: The stack type chip inductor is formed of a number of ceramic sheets(1,2,3,4,5) stacked by turns. Conductive patterns(11,12,13,14,15), playing as a coil and electrically connected each other, are formed on the ceramic sheets(1,2,3,4,5), respectively. From the ceramic sheets(1,2,3,4,5), a conductive pattern(11) formed on a first ceramic sheet(1) placed at bottom and a conductive pattern(12) formed on a second ceramic sheet(2) placed at top have a same shape and are arranged to make a rotation symmetry about center of the ceramic sheet. Especially, the first and second ceramic sheets(1,2) are arranged to make 180 degree rotation symmetry, and one or more third ceramic sheet(s) is/are stacked between the first and second ceramic sheets. The third ceramic sheet(3) has a conductive pattern(13) electrically connected to the conductive patterns(11,12) of the first and second ceramic sheets.

Abstract translation: 目的：提供堆叠型片式电感器，通过减少形成在叠层型片式电感器的陶瓷片上的导电图案的掩模数量来减少成本和工艺数量。 构成：堆叠型芯片电感由多个堆叠的陶瓷片（1,2,3,4,5）组成。 在陶瓷片（1,2,3,4,5）上分别形成作为线圈并彼此电连接的导电图案（11,12,13,14,15）。 从陶瓷片（1,2,3,4,5）中，形成在位于底部的第一陶瓷片（1）上的导电图案（11）和形成在第二陶瓷片（2）上的导电图案（12） 放置在顶部具有相同的形状并被布置成围绕陶瓷片的中心旋转对称。 特别地，第一和第二陶瓷片（1,2）被布置成使180度旋转对称，并且在第一和第二陶瓷片之间堆叠一个或多个第三陶瓷片。 第三陶瓷片（3）具有与第一和第二陶瓷片的导电图案（11,12）电连接的导电图案（13）。

公开(公告)号：KR100213937B1

公开(公告)日：1999-08-02

申请号：KR1019960025192

申请日：1996-06-28

Applicant: 전자부품연구원

Inventor： 장동석 ,  강남기 ,  조형진

IPC: H01F1/16

Abstract: 본 발명은 칩 인덕터에 관한 것으로, 특히 회로기판에 직접 접촉고정되는 부분인 칩 인덕터의 외부전극 부분의 기계적 강도가 증진되도록한 칩 인덕터에 관한 것으로, 비어홀이 천공되고 내부 전극이 인쇄된 각 그린시트와 소정 위치에 핀홀을 가공하고 인쇄패턴이 형성되지 않은 그린시트를 적층, 가열함으로써, 내부전극을 형성하고, 상기 핀홀을 통하여 내부전극과 전기적으로 접속하는 외부전극을 상기 내부전극의 측부에 형성하여, 상기 내부 전극이 상기 핀홀과 측부의 노출 내부전극패턴을 통해 칩 인덕터의 외부 전극에 접속되며, 상기 핀홀에 도전성 페이스트가 충진된다.