公开(公告)号：KR1020090059795A

公开(公告)日：2009-06-11

申请号：KR1020070126841

申请日：2007-12-07

Applicant: 한국전자통신연구원

Inventor： 안호균 ,  임종원 ,  지홍구 ,  장우진 ,  문재경 ,  김해천 ,  유현규

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76897

Abstract: A manufacturing method of a multilayer metal wiring is provided to stably manufacture a multilayer metal wiring and to reduce possibility of misalignment by forming a pattern through one exposure. A source drain ohmic metal layer is formed by depositing an ohmic metal(130) on a semiconductor substrate having an active layer and a cap layer. A first insulation film(140) is deposited on a whole surface of the semiconductor substrate. A first multilayer photoresist is deposited in consideration of an etching selection ratio with the first insulation film. A first metal wiring(170a) is formed by depositing a metal on a first pattern region. A second insulation film(180) is formed on a whole surface of the substrate having the first metal wiring. A second multilayer photoresist(150b,160b) is deposited in consideration of an etching selection ratio with the second insulation film. A second metal wiring(170b) is formed by depositing a metal on a second pattern region. A protective film is deposited on the second metal wiring.

Abstract translation: 提供多层金属布线的制造方法，以稳定地制造多层金属布线，并通过一次曝光形成图案来减少不对准的可能性。 源极欧姆金属层通过在具有有源层和盖层的半导体衬底上沉积欧姆金属（130）而形成。 第一绝缘膜（140）沉积在半导体衬底的整个表面上。 考虑到与第一绝缘膜的蚀刻选择比，沉积第一多层光致抗蚀剂。 通过在第一图案区域上沉积金属来形成第一金属布线（170a）。 在具有第一金属布线的基板的整个表面上形成第二绝缘膜（180）。 考虑到与第二绝缘膜的蚀刻选择比，沉积第二多层光致抗蚀剂（150b，160b）。 通过在第二图案区域上沉积金属来形成第二金属布线（170b）。 保护膜沉积在第二金属布线上。

公开(公告)号：KR1020090059450A

公开(公告)日：2009-06-11

申请号：KR1020070126316

申请日：2007-12-06

Applicant: 한국전자통신연구원

Inventor： 김동영 ,  문재경 ,  김해천 ,  유현규

IPC: H01P3/08

CPC classification number: H01P3/08 ,  H01P1/2136 ,  H01P5/19

Abstract: An ultra-high frequency transmitting device is provided to relieve discontinuity of electric field in a junction region between a strip transmission line and a micro strip transmission line by using a signal matching ground. An ultra-high frequency transmitting device includes a strip transmission line(strip), a micro strip transmission line(Mstrip), and a signal matching ground(Stuning). The strip transmission line is arranged inside a multilayer substrate. The micro strip transmission line is arranged outside the multilayer substrate. The micro strip transmission line is connected to the strip transmission line. The signal matching ground is positioned in a bottom surface of the micro strip transmission line. The signal matching ground is extended from the micro strip transmission line to the strip transmission line. The signal matching ground is connected to a ground(GND2) positioned in a bottom layer of the multilayer substrate.

Abstract translation: 提供了一种超高频发射装置，通过使用信号匹配地来缓解带状传输线和微带传输线之间的接合区域中的电场的不连续性。 超高频发送装置包括带状传输线（条），微带传输线（Mstrip）和信号匹配接地（Stuning）。 带状传输线设置在多层基板内。 微带传输线布置在多层基板的外侧。 微带传输线连接到条传输线。 信号匹配接地位于微带传输线的底面。 信号匹配接地从微带传输线延伸到带状传输线。 信号匹配地连接到位于多层基板的底层中的地（GND2）。

公开(公告)号：KR100857469B1

公开(公告)日：2008-09-08

申请号：KR1020070025080

申请日：2007-03-14

Applicant: 한국전자통신연구원

Inventor： 김동영 ,  문재경 ,  전동석 ,  김해천

IPC: H01P5/107 ,  H01P3/08 ,  H01P3/00

Abstract: 본 발명은 밀리미터파 대역 전송특성을 향상시키기 위한 변환기가 구비된 초고주파 모듈에 관한 것으로, 마이크로스트립 전송선로와 CBCPW 전송선로를 와이어 본딩을 이용하여 연결할 경우, 와이어 본딩에 의한 임피던스 변화와 두 전송선로 사이의 전계성분의 급격한 변화를 변환기를 통해 완화시켜 삽입손실 및 반사손실이 감소되도록 함으로써, 밀리미터파 대역의 전송특성을 향상시키는 것을 특징으로 한다.
밀리미터파 대역, 와이어 본딩, 변환기, 마이크로스트립, CBCPW, SOP

公开(公告)号：KR1020080052223A

公开(公告)日：2008-06-11

申请号：KR1020070054263

申请日：2007-06-04

Applicant: 한국전자통신연구원

Inventor： 김용원 ,  유현규 ,  김해천 ,  임종원 ,  오명숙

IPC: H01L31/10

CPC classification number: H01L31/10 ,  H01L31/022425 ,  H01L31/02366 ,  H01L31/03046 ,  H01L31/18

Abstract: A Pin photodiode is provided to reduce the leakage current of a pin photodiode with a wave guide by forming a metal layer on a wafer guide pattern. A first semiconductor layer, an absorption layer, a second semiconductor layer, a photo clad layer and a photo cap layer are formed on a substrate(31). After a first insulation layer is formed on the photo cap layer, the first insulation layer is patterned by using a photoresist pattern formed on the first insulation layer. The photo cap layer, the photo clad layer, the second semiconductor layer and the absorption layer are etched by using the patterned first insulation layer as a mask. After the pattern first insulation layer is removed, a second insulation layer is formed on the patterned photo cap layer and the patterned first semiconductor layer. After a photoresist pattern is formed on the second insulation layer, the second insulation layer is patterned by using the photoresist pattern. The semiconductor layer is patterned by using the patterned second insulation layer. After the patterned second insulation layer is removed, a first electrode(41) is formed on the photo cap layer and the first semiconductor layer. After a polyimide layer can be formed on a partial region of the substrate, the polyimide layer is patterned and a second electrode(43) is formed on the patterned polyimide layer.

Abstract translation: 提供引脚光电二极管，通过在晶片引导图案上形成金属层来减小波导管的引脚光电二极管的漏电流。 在基板（31）上形成有第一半导体层，吸收层，第二半导体层，光覆层和光电盖层。 在光罩层上形成第一绝缘层之后，通过使用形成在第一绝缘层上的光致抗蚀剂图案来对第一绝缘层进行构图。 通过使用图案化的第一绝缘层作为掩模来蚀刻光封层，光覆层，第二半导体层和吸收层。 在去除图案第一绝缘层之后，在图案化的光罩层和图案化的第一半导体层上形成第二绝缘层。 在第二绝缘层上形成光致抗蚀剂图案之后，通过使用光致抗蚀剂图案来对第二绝缘层进行图案化。 通过使用图案化的第二绝缘层来图案化半导体层。 在去除图案化的第二绝缘层之后，在光电帽层和第一半导体层上形成第一电极（41）。 在可以在基板的部分区域上形成聚酰亚胺层之后，对该聚酰亚胺层进行图案化，并且在图案化的聚酰亚胺层上形成第二电极（43）。

公开(公告)号：KR100576708B1

公开(公告)日：2006-05-03

申请号：KR1020030087994

申请日：2003-12-05

Applicant: 한국전자통신연구원

Inventor： 문재경 ,  지홍구 ,  안호균 ,  김해천

IPC: H01L27/095

CPC classification number: H01L29/7785

Abstract: 이중 면도핑 구조를 가지는 에피 기판으로부터 얻어진 고전력, 저삽입손실, 고격리도, 고스위칭속도를 갖는 고주파 스위치 소자에 관하여 개시한다. 본 발명에 따른 고주파 스위치 소자는, GaAs 반절연 기판 상에 AlGaAs/GaAs 초격자 버퍼층, 제1 Si 면도핑층, 도핑되지 않은 제1 AlGaAs 스페이서, 도핑되지 않은 InGaAs층, 도핑되지 않은 제2 AlGaAs 스페이서, 상기 제1 Si 면도핑층보다 큰 도핑 농도를 가지는 제2 Si 면도핑층 및 도핑되지 않은 GaAs/AlGaAs 캡층이 차례로 적층된 에피 기판을 포함한다. 상기 도핑되지 않은 GaAs/AlGaAs 캡층 위에는 상기 도핑되지 않은 GaAs/AlGaAs 캡층과 오믹 콘택을 형성하는 소오스 전극 및 드레인 전극이 형성되어 있다. 상기 소오스 전극 및 드레인 전극 사이에는 상기 도핑되지 않은 GaAs/AlGaAs 캡층과 쇼트키 콘택을 형성하는 게이트 전극이 형성되어 있다.

公开(公告)号：KR1020050055204A

公开(公告)日：2005-06-13

申请号：KR1020030088259

申请日：2003-12-05

Applicant: 한국전자통신연구원

Inventor： 장우진 ,  김해천

IPC: H01P3/12

CPC classification number: H01P1/022 ,  H01P1/042

Abstract: 본 발명은 도파관이 직각으로 연결되는 부분에서 모서리인 불연속 지점에 의해 발생하는 비정합에 의해 신호의 반사 및 손실이 일어나는 것을 감소시키기 위하여 직각으로 연결되는 부분을 곡면 구조로 제작하여 신호의 반사 및 손실을 개선시키기 위한 것이다.
본 발명에 따르면, 도파관 구조를 갖는 초고주파 패키지 내부의 상호연결을 위한 저손실의 도파관 연결장치을 구현가능하고, 동일 칩과 동일 구조에서 기존 방법에 비해 우수한 성능의 패키지 제품을 생산할 수 있다.

公开(公告)号：KR100444820B1

公开(公告)日：2004-08-18

申请号：KR1020010047655

申请日：2001-08-08

Applicant: 한국전자통신연구원

Inventor： 남은수 ,  임종원 ,  박민 ,  김해천

IPC: H01L31/12

Abstract: PURPOSE: A photodetector is provided to minimize a tunneling leakage current and improve the capability of a light receiving chip in which the photodetector and a hetero-junction bipolar transistor are integrated into a single chip, by smoothly transferring the charges generated in a light absorbing layer. CONSTITUTION: The first conductive layer of the first conductivity type is formed in a predetermined region on a substrate(40). A light absorbing layer(43) is stacked on the first conductive layer. The second conductive layer of the second conductivity type is stacked on the light absorbing layer. The third conductive layer are formed between the first conductive layer and the light absorbing layer and between the light absorbing layer and the second conductive layer, decreasing a lattice match and a potential energy band difference between the two stack layers to make photoelectrons flow smoothly.

Abstract translation: 目的：提供一种光电探测器，以最小化隧道泄漏电流，并通过将光吸收层中产生的电荷平稳地转移到光电探测器中，从而提高其中光电探测器和异质结双极晶体管集成到单个芯片中的光接收芯片的能力 。 构成：第一导电类型的第一导电层形成在衬底（40）上的预定区域中。 光吸收层（43）堆叠在第一导电层上。 第二导电类型的第二导电层堆叠在光吸收层上。 所述第三导电层形成于所述第一导电层与所述光吸收层之间以及所述光吸收层与所述第二导电层之间，减少所述两层叠层之间的晶格匹配和势能差，使光电子顺利流动。

公开(公告)号：KR1020030092749A

公开(公告)日：2003-12-06

申请号：KR1020020030541

申请日：2002-05-31

Applicant: 한국전자통신연구원

Inventor： 남은수 ,  김해천

IPC: H01L29/737

CPC classification number: B82Y20/00 ,  H01L31/035236 ,  H01L31/105

Abstract: PURPOSE: An optical receiver that selectively detects light of a specific wavelength is provided to selectively detect an optical signal of a specific wavelength and amplify a converted electrical signal by integrating a waveguide-type optical detector and an n+InP/p+InGaAs/n-InGaAs/n+InGaAsP heterojunction bipolar transistor(HBT) on a half-insulated InP substrate wherein the optical detector uses a quantum well structure as a light absorbing layer and the HBT amplifies an electrical signal converted by the optical detector. CONSTITUTION: A p+InGaAsP layer(202), an i-InGaAsP/i-InGaAsP layer(203) of a multi quantum well structure and an n+InGaAsP sub-collector layer(204) are stacked in a predetermined region on the half-insulated InP substrate(201). An n-InGaAs layer and a p+InGaAs base layer are stacked in a predetermined region on the n+InGaAsP sub-collector layer to transfer high speed current. An n+InP emitter layer and an n+InGaAs ohmic layer are stacked in a predetermined region on the p+InGaAs base layer. An emitter electrode(211) is formed on the n+InGaAs ohmic layer. A base electrode(212) is formed in a predetermined region on the p+InGaAs base layer. A collector electrode(213) is formed in a predetermined region on the n+InGaAsP sub-collector layer.

Abstract translation: 目的：提供选择性地检测特定波长的光的光学接收器，以选择性地检测特定波长的光信号，并通过集成波导型光学检测器和n + InP / p + InGaAs / n来放大转换的电信号 在半绝缘InP衬底上的InGaAs / n + InGaAsP异质结双极晶体管（HBT），其中光学检测器使用量子阱结构作为光吸收层，并且HBT放大由光学检测器转换的电信号。 构成：多量子阱结构的p + InGaAsP层（202），i-InGaAsP / i-InGaAsP层（203）和n + InGaAsP子集电极层（204）堆叠在一半的预定区域 - 绝缘InP衬底（201）。 在n + InGaAsP子集电极层上的预定区域中堆叠n-InGaAs层和p + InGaAs基层以传送高速电流。 在p + InGaAs基层上的预定区域中堆叠n + InP发射极层和n + InGaAs欧姆层。 在n + InGaAs欧姆层上形成发射电极（211）。 在p + InGaAs基层的规定区域形成有基极（212）。 集电极（213）形成在n + InGaAsP副集电极层的规定区域。

公开(公告)号：KR1020030042791A

公开(公告)日：2003-06-02

申请号：KR1020010073570

申请日：2001-11-24

Applicant: 한국전자통신연구원

Inventor： 김성일 ,  임종원 ,  김해천

IPC: G02B6/42

CPC classification number: G02B6/4201 ,  G02B6/4274 ,  G02B6/4279 ,  H01L2224/48091 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PURPOSE: A sub mount for photoelectric module and a mounting method using the same are provided to enhance an electrical characteristic by using a signal connection line of a co-planar waveguide structure. CONSTITUTION: A sub mount(200) for converting an incident ray of a photoelectric element(230) to an electric signal includes a dielectric(210) and a signal connection line(220). The dielectric has a front side(211) and a bottom side(212). The signal connection line is adhered on the front side and the bottom side. The signal connection line is electrically connected with the photoelectric element in order to output the electric signal from the photoelectric element. The signal connection line having a co-planar waveguide structure includes a plurality of signal connection lines. The plural signal connection lines include the first ground line(221), a signal transmission line(222), the second ground line(223), and a bias application line(224).

Abstract translation: 目的：提供一种用于光电模块的辅助安装座及其安装方法，以通过使用共面波导结构的信号连接线来增强电气特性。 构成：用于将光电元件（230）的入射光线转换为电信号的副安装座（200）包括电介质（210）和信号连接线（220）。 电介质具有前侧（211）和底侧（212）。 信号连接线粘附在前侧和底侧。 信号连接线与光电元件电连接，以便从光电元件输出电信号。 具有共平面波导结构的信号连接线包括多个信号连接线。 多个信号连接线包括第一接地线（221），信号传输线（222），第二接地线（223）和偏置施加线（224）。

公开(公告)号：KR100385856B1

公开(公告)日：2003-06-02

申请号：KR1020000082810

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 문재경 ,  김해천 ,  임종원

IPC: H01L21/335

CPC classification number: H01L29/66848

Abstract: The present invention provides a self-aligned gate transistor. The present invention implants P-type impurity ions only below a channel region below a gate and below a source and drain electrode on semiconductor substrate having an ion implantation channel layer without implanting the P-type impurity ions into a narrow region between the source-gate and the gate-drain, deposits a gate metal and etches the gate pattern. In this case, the length (Lg) of the gate is defined to be narrower than the length (Lch-g) into which P-type impurity ions are implanted below the channel layer, thus improving a pinch-off characteristic. A method of manufacturing a field effect transistor having a self aligned gate according to the present invention comprises the steps of implanting P-type impurity ions only below a channel region below a gate and below a source and drain electrode; and depositing a refractory gate metal having a good high temperature stability to form a gate pattern using a dry etch method.

Abstract translation: 本发明提供了一种自对准栅极晶体管。 本发明仅在具有离子注入沟道层的半导体衬底上的栅极下方的沟道区下方以及源极和漏极下方的P型杂质离子注入P型杂质离子，而不将P型杂质离子注入到源极栅极 和栅极 - 漏极，沉积栅极金属并蚀刻栅极图案。 在这种情况下，栅极的长度（Lg）被限定为比在沟道层下方注入P型杂质离子的长度（Lch-g）窄，因此改善了夹断特性。 根据本发明的制造具有自对准栅极的场效应晶体管的方法包括以下步骤：仅在栅极下面的沟道区下面以及源极和漏极下面注入P型杂质离子; 以及使用干蚀刻方法沉积具有良好高温稳定性的耐火栅极金属以形成栅极图案。