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公开(公告)号：KR1020120041002A
公开(公告)日：2012-04-30
申请号：KR1020100102547
申请日：2010-10-20
Applicant: 한국전자통신연구원 , 고려대학교 산학협력단
IPC: G06T7/00
CPC classification number: G06K9/4642 , G06K9/3241
Abstract: PURPOSE: An object detecting device and a system thereof are provided to form a feature vector by using HOG(Histogram of Oriented Gradients) and pixel coordinate information . CONSTITUTION: An outline image extracting unit(120) extracts an outline image from an input image. A feature vector calculating unit(130) calculates a feature vector from the outline image by using HOG and pixel coordinate information. The HOG displays frequency distribution of gradient vectors for pixels in the outline image. The pixel coordinate information is changed by spatial distribution of the gradient vectors. An object determining unit(150) determines a target object corresponding to the feature vector referring to pre-learned data.
Abstract translation: 目的：提供一种物体检测装置及其系统，通过使用HOG（定向梯度直方图）和像素坐标信息形成特征向量。 构成：轮廓图像提取单元（120）从输入图像中提取轮廓图像。 特征向量计算单元（130）通过使用HOG和像素坐标信息从轮廓图像计算特征向量。 HOG显示轮廓图像中像素的梯度向量的频率分布。 通过梯度矢量的空间分布来改变像素坐标信息。 对象确定单元（150）参考预先学习的数据来确定与特征向量相对应的目标对象。
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公开(公告)号：KR1020120038764A
公开(公告)日：2012-04-24
申请号：KR1020100100399
申请日：2010-10-14
Applicant: 한국전자통신연구원
CPC classification number: H04N7/183 , G06K9/6203
Abstract: PURPOSE: An image recognition method and an image recognition device thereof are provided to offer additional memory to store a standard image and a reduced image. CONSTITUTION: An image recognition device selects a part of data from standard image data(S110). The image recognition device recognizes an image based on selected data(S120). The image recognition device reduces the selected data(S130). The image recognition device recognizes the image based on the reduced data(S140).
Abstract translation: 目的：提供图像识别方法及其图像识别装置，以提供用于存储标准图像和缩小图像的附加存储器。 构成：图像识别装置从标准图像数据中选择一部分数据（S110）。 图像识别装置基于所选择的数据识别图像（S120）。 图像识别装置减少所选择的数据（S130）。 图像识别装置基于减少的数据识别图像（S140）。
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公开(公告)号：KR101114493B1
公开(公告)日：2012-02-27
申请号：KR1020080131861
申请日：2008-12-23
Applicant: 한국전자통신연구원 , 광운대학교 산학협력단
Abstract: 본 발명은 프로세서에 관한 것으로, 더욱 상세하게는 다중표준 가변길이부호 코덱을 처리하는 비트스트림 프로세서에 관한 것이다.
본 발명에 따른 비트스트림 프로세서는 비트스트림을 구문처리하여 런 값과 레벨 값을 출력하는 신택스 프로세서; 복수의 지그재그 스캔 순서들을 저장하는 지그재그 테이블; 및 상기 런 값과 레벨 값을 입력받아 런레벨 디코딩을 실행하고, 상기 복수의 지그재그 스캔 순서들 중 상기 비트스트림의 코덱에 해당하는 지그재그 순서에 따라 상기 실행 결과를 저장하는 런레벨 프로세서를 포함하고, 상기 신택스 프로세서는 새로운 지그재그 스캔 순서를 상기 지그재그 테이블에 저장한다. 따라서, 본 발명에 따른 비트스트림 프로세서는 하드와이어드 로직으로 구현된 런레벨 프로세서를 포함하여 성능을 향상시키고, 복수의 지그재그 스캔 순서를 저장하는 테이블을 제어하는 신택스 프로세서를 포함하여 다중 표준 코덱을 지원할 수 있다.-
Patent Agency Ranking
公开(公告)号：KR1020110067359A
公开(公告)日：2011-06-22
申请号：KR1020090123928
申请日：2009-12-14
Applicant: 한국전자통신연구원 , 안동대학교 산학협력단
CPC classification number: B62D15/0265 , B60W30/12 , B60W30/18163 , G06K9/00798 , G06K9/00805 , G08G1/16 , G08G1/166 , G08G1/167 , Y02T10/84
Abstract: PURPOSE: An apparatus for preventing vehicle collision is provided to simply prevent vehicle collision without complex function calculation. CONSTITUTION: An apparatus for preventing vehicle collision comprises: an image data acquiring unit which photographs external images including other vehicles and acquires external image data; an image recognition unit which analyzes external image data and recognizes user's vehicle, lane, and other vehicles; a drive information determination unit; and a control unit which generates and outputs controlling signal.
Abstract translation: 目的：提供一种防止车辆碰撞的装置，以简单地防止车辆碰撞，而无需复杂的功能计算。 一种用于防止车辆碰撞的装置，包括：图像数据获取单元，其拍摄包括其他车辆的外部图像并获取外部图像数据; 图像识别单元，其分析外部图像数据并识别用户的车辆，车道和其他车辆; 驱动信息确定单元; 以及产生并输出控制信号的控制单元。
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公开(公告)号：KR1020100073243A
公开(公告)日：2010-07-01
申请号：KR1020080131863
申请日：2008-12-23
Applicant: 한국전자통신연구원 , 광운대학교 산학협력단
IPC: H03M7/40
Abstract: PURPOSE: A method for driving a bitstream processor is provided to efficiently process the variable data of a continuous bitstream by using a bitstream dedicated instruction. CONSTITUTION: A bitstream processor(110) converts a read bitstream into the bitstream following an abbreviated table lookup, and an execution unit(120) converts a bit-stream into a table lookup following. An instruction fetch unit(130) fetches a command related to the bitstream accoridng to a PC(Program Counter) of a processor controller(140). The processor control unit controls the bitstream processor and the execution unit.
Abstract translation: 目的：提供一种用于驱动比特流处理器的方法，以通过使用比特流专用指令来有效地处理连续比特流的可变数据。 构成：比特流处理器（110）在缩写表查找之后将读取比特流转换为比特流，并且执行单元（120）将比特流转换成以下的表查找。 指令提取单元（130）提取与根据处理器控制器（140）的PC（程序计数器）相关的比特流的命令。 处理器控制单元控制比特流处理器和执行单元。
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公开(公告)号：KR1020100072614A
公开(公告)日：2010-07-01
申请号：KR1020080131065
申请日：2008-12-22
Applicant: 한국전자통신연구원
CPC classification number: G06F1/3203 , G06F1/3287 , G06F1/3296 , Y02D10/171 , Y02D10/172 , Y02D50/20
Abstract: PURPOSE: A processor with low power is provided to activate at least one among core block, a memory, a peripheral block by responding to a signal which activates according to an address map, thereby preventing a power consumption. CONSTITUTION: A low power processor comprises a plurality of blocks(30,70), a memory(50), and a multi power control unit(10). The memory stores a command for controlling the plurality of blocks. According to an address, the multi power control unit generates a signal for activating at least one among the plurality of blocks. By responding to the activation signal, the multi power control unit provides a normal power voltage or reduction power voltage. A command is stored in a relevant address.
Abstract translation: 目的：提供低功耗的处理器，通过响应根据地址映射激活的信号来激活核心块，存储器，外围块中的至少一个，从而防止功耗。 构成：低功率处理器包括多个块（30,70），存储器（50）和多功率控制单元（10）。 存储器存储用于控制多个块的命令。 根据地址，多功率控制单元生成用于激活多个块中的至少一个的信号。 通过响应激活信号，多功率控制单元提供正常的电源电压或降低功率电压。 命令存储在相关地址中。
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公开(公告)号：KR1020100063620A
公开(公告)日：2010-06-11
申请号：KR1020090031777
申请日：2009-04-13
Applicant: 한국전자통신연구원
IPC: H04N19/147 , H04N19/103 , H04N19/51
CPC classification number: H04N19/567 , H04N19/105
Abstract: PURPOSE: An image processing apparatus is provided, which firstly decides the optimal encoding mode, and then, proceeds the other processes such as the motion estimation and compensation, quantization, the variable length coding and inverse quantization etc. CONSTITUTION: A control unit(101) stores the generated bit amount for the computation of the Rate Distortion cost value. The control unit transmits respectively the generated bit amount to a plurality of operation units(110,120,130,140). At least one among a plurality of operation units produces each degree of distorted value about a plurality of encoding modes. The control unit calculates each distorted cost value about a plurality of encoding modes by the calculated distorted value and the generated bit amount.
Abstract translation: 目的：提供一种图像处理装置，其首先确定最佳编码模式，然后进行诸如运动估计和补偿，量化，可变长度编码和反量化等的其他处理。构成：控制单元（101 ）存储用于计算速率失真成本值的生成位数。 控制单元将产生的位量分别发送到多个操作单元（110,120,130,140）。 多个操作单元中的至少一个产生关于多个编码模式的每个程度的失真值。 控制单元通过计算出的失真值和产生的位量来计算关于多个编码模式的每个失真成本值。
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公开(公告)号：KR1020090058657A
公开(公告)日：2009-06-10
申请号：KR1020070125348
申请日：2007-12-05
Applicant: 한국전자통신연구원
IPC: G06F7/57
CPC classification number: G06F7/57 , G06F7/5324 , G06F7/5338
Abstract: A reconfigurable arithmetic operator and a high efficiency processor with the same are provided to supply an arithmetic operator operating as an adder or a multiplier according to an instruction, thereby increasing hardware utilization. A reconfigurable arithmetic operator comprises a booth encoder(210), a partial product generator(220), a wallace tree circuit(230), the first register(241), the second register(242), the first MUX(251), the second MUX(252), and a CPA(Carry Propagation Adder)(260). The partial product generator generates a partial product based on encoded multiplier and multilplicand. The CPA performs an addition operation by using outputs of the first and second MUXs.
Abstract translation: 提供可重构算术运算器和具有该可重配算术运算器的高效处理器，以根据指令提供作为加法器或乘法器运算的算术运算器，从而增加硬件利用率。 可重构算术运算器包括展位编码器（210），部分乘积产生器（220），华莱士树电路（230），第一寄存器（241），第二寄存器（242），第一多路复用器（251） 第二MUX（252）和CPA（Carry Propagation Adder）（260）。 部分产品生成器基于编码乘数和多项式生成部分乘积。 CPA通过使用第一和第二MUX的输出执行相加操作。
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