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    83.
    发明专利
    未知

    公开(公告)号：DE69828547T2

    公开(公告)日：2005-12-22

    申请号：DE69828547

    申请日：1998-06-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOENIGSCHMID HEINZ

    IPC: H01L27/108 ,  G11C7/12 ,  G11C11/4094 ,  H01L21/8242 ,  G11C11/409 ,  G11C7/00

    Abstract: An equalizer circuit for precharging a pair of bit lines in a dynamic random access memory circuit. The equalizer circuit includes a substantially T-shaped polysilicon gate portion oriented at an angle relative to the pair of bit lines. The angle is an angle other than an integer multiple of 90 DEG . The substantially T-shaped polysilicon gate portion includes first polysilicon area for implementing a gate of a first switch of the equalizer circuit. The first switch is coupled to a first bit line of the pair of bit lines and a second bit line of the pair of bit lines. The substantially T-shaped polysilicon gate portion also includes a second polysilicon area for implementing a gate of a second switch of the equalizer circuit. The second switch is coupled to the first bit line of the pair of bit lines and a precharge voltage source. The substantially T-shaped polysilicon gate portion further includes a third polysilicon area for implementing a gate of a third switch of the equalizer circuit. The third switch is coupled to the second bit line of the pair of bit lines and the precharge voltage source.

    85.
    发明专利
    未知

    公开(公告)号：DE60300777D1

    公开(公告)日：2005-07-07

    申请号：DE60300777

    申请日：2003-02-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOENIGSCHMID HEINZ ,  VIEHMANN HANS-HEINRICH

    IPC: G11C29/04 ,  G11C17/14 ,  G11C29/00 ,  G11C29/44

    Abstract: It is difficult to fabricate a semiconductor memory device without any faulty memory storage cells. One solution is to produce more storage cells than needed on a device and faulty storage cells are replaced by the redundant storage cells. This solution requires that the addresses of the faulty storage cells, along with the replacement storage cells, be saved in a memory. The present invention teaches the use of non-volatile memory cells, particularly magnetoresistive random access memory (MRAM) cells, to store the addresses. Non-volatile memory cells can effectively replace the laser fuses currently used and also provides an advantage in the elimination of the laser fuse-burning step during the fabrication of the device.

    86.
    发明专利
    未知

    公开(公告)号：DE50105919D1

    公开(公告)日：2005-05-19

    申请号：DE50105919

    申请日：2001-09-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

    IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

    Abstract: An integrated magnetoresistive semiconductor memory system, in which n memory cells that contain two magnetic layers each separated by a thin dielectric barrier, and associated word lines and bit lines that cross one another are vertically stacked in n layers. The system further contains a decoding circuit for selecting one of the n memory layers. The decoding circuit, on both ends of a word line or a bit line, is provided with one configuration each that contains n layer selecting transistors for selecting one of the n memory layers, and with a line selection transistor for selecting the respective horizontal word line or bit line on which a voltage is to be impressed.

    87.
    发明专利
    未知

    公开(公告)号：DE59910447D1

    公开(公告)日：2004-10-14

    申请号：DE59910447

    申请日：1999-12-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOENIGSCHMID HEINZ ,  BRAUN GEORG ,  MANYOKI ZOLTAN ,  ROEHR DR ,  BOEHM THOMAS

    IPC: G11C8/00 ,  G11C8/10 ,  H03K19/084 ,  H03K19/094 ,  H03K19/23 ,  H03M5/16

    Abstract: An integrated circuit includes a decoder having an output terminal and five input terminals. The decoder has three operating states including a first operating state for generating a first potential at the output terminal, a second operating state for generating a second potential at the output terminal, and a third operating state for generating a third potential at the output terminal. The second potential lies between the first potential and the third potential.

    90.
    发明专利
    未知

    公开(公告)号：DE59905214D1

    公开(公告)日：2003-05-28

    申请号：DE59905214

    申请日：1999-07-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRAUN GEORG ,  HOENIGSCHMID HEINZ

    IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502

    Abstract: A ferroelectric storage assembly containing a storage cell array composed of a plurality of storage cells is described. Each storage cell contains at least one selector transistor and a storage capacitor, and can be controlled via word lines and bit lines. A short-circuit transistor is located over each storage capacitor in order to protect the storage.

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