公开(公告)号：DE112013003193T5

公开(公告)日：2015-03-19

申请号：DE112013003193

申请日：2013-06-10

Applicant: INTEL CORP

Inventor： LIN KEVIN L ,  MA QING ,  EID FERAS ,  SWAN JOHANNA M ,  TEH WENG HONG

IPC: H01L25/07 ,  H01L25/065

Abstract: Ein Halbleitergehäuse, das einen Luftdrucksensor aufweist, sowie Verfahren zum Ausbilden eines Halbleitergehäuses, das einen Luftdrucksensor aufweist, sind beschrieben. Zum Beispiel umfasst ein Halbleitergehäuse eine Vielzahl von Aufbauschichten. Eine Kavität ist in einer oder mehreren der Aufbauschichten angeordnet. Ein Luftdrucksensor ist in der Vielzahl von Aufbauschichten angeordnet und umfasst die Kavität und eine über der Kavität angeordnete Elektrode. Außerdem sind verschiedene Ansätze zum Herstellen eines Halbleitergehäuses beschrieben, das einen hermetisch versiegelten Bereich aufweist.

公开(公告)号：GB2511704A

公开(公告)日：2014-09-10

申请号：GB201411223

申请日：2013-06-20

Applicant: INTEL CORP

Inventor： LIN KEVIN ,  EID FARAS ,  MA QING

IPC: G01P15/105 ,  B81B3/00 ,  G01C19/56

Abstract: Techniques and mechanisms to provide for metering acceleration. In an embodiment, a microelectromechanical accelerometer includes a magnet, a mass, and a first support beam portion and second support beam portion for suspension of the mass. Resonance frequency characteristics of the first support beam portion and second support beam portion, based on the magnet and a current conducted by the first support beam portion and second support beam portion, are indicative of acceleration of the mass. In another embodiment, the accelerometer further includes a first wire portion and a second wire portion which are each coupled to the mass and further coupled to a respective anchor for exchanging a signal with the first wire portion and the second wire portion. The first wire portion and the second wire portion provide for biasing of the mass.

公开(公告)号：DE112010004888T5

公开(公告)日：2012-10-18

申请号：DE112010004888

申请日：2010-11-01

Applicant: INTEL CORP

Inventor： MA QING ,  HU CHUAN ,  MORROW PATRICK

IPC: H01L23/485 ,  H05K3/46

Abstract: Es werden Ausführungsformen eines Substrats für einen IC(Integrated Circuit)-Baustein offenbart. Das Substrat enthält einen Kern, der aus zwei oder mehr diskreten Glasschichten besteht, die miteinander verbondet wurden. Eine separate Bondungsschicht kann zwischen benachbarten Glasschichten angeordnet werden, um diese Schichten miteinander zu koppeln. Das Substrat kann außerdem Aufbaustrukturen auf gegenüberliegenden Seiten des Mehrschichtglaskerns oder eventuell auf einer Seite des Kerns enthalten. Elektrisch leitfähige Anschlüsse können auf beiden Seiten des Substrats ausgebildet werden, und ein IC-Chip kann auf einer Seite des Substrats mit den Anschlüssen gekoppelt werden. Die Anschlüsse auf der gegenüberliegenden Seite können mit einer Komponente der nächsten Ebene, wie zum Beispiel einer Leiterplatte, gekoppelt werden. Ein oder mehrere Leiter erstrecken sich durch den Mehrschichtglaskern, und ein oder mehrere der Leiter können elektrisch mit den über dem Kern angeordneten Aufbaustrukturen gekoppelt sein. Es werden noch weitere Ausführungsformen beschrieben und beansprucht.

公开(公告)号：GB2488265A

公开(公告)日：2012-08-22

申请号：GB201208343

申请日：2010-11-01

Applicant: INTEL CORP

Inventor： MA QING ,  HU CHUAN ,  MORROW PATRICK

IPC: H01L23/485 ,  H05K3/46

Abstract: Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.

公开(公告)号：GB2447158B

公开(公告)日：2011-03-02

申请号：GB0807714

申请日：2006-12-06

Applicant: INTEL CORP

Inventor： RAO VALLURI ,  DOROS THEODORE G ,  MA QING ,  SESHAN KRISHNA ,  WANG LI-PENG

IPC: H03H3/04 ,  H03H9/02 ,  H03H9/17 ,  H03H9/58

Abstract: Multiple FBARs may be manufactured on a single wafer and later diced. Ideally, all devices formed in a wafer would have the same resonance frequency. However, due to manufacturing variances, the frequency response of the FBAR devices may vary slightly across the wafer. An RF map may be created to determine zones over the wafer where FBARs in that zone all vary from a target frequency by a similar degree. A tuning layer may be deposited over the wafer. Lithographically patterned features to the tuning layer based on the zones identified by the RF map may be used to correct the FBARs to a target resonance frequency with the FBARs still intact on the wafer.

公开(公告)号：GB2453283A

公开(公告)日：2009-04-01

申请号：GB0822743

申请日：2007-06-26

Applicant: INTEL CORP

Inventor： MA QING ,  CHOU TSUNG-KUAN ALLEN

IPC: H01L45/00 ,  B81B3/00 ,  G11C16/02 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L27/24

Abstract: An apparatus comprising a substrate, a heater formed on the substrate, and a phase-change layer formed on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. A process comprising forming a heater on a substrate and forming a phase-change layer on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer.

公开(公告)号：DE602005012601D1

公开(公告)日：2009-03-19

申请号：DE602005012601

申请日：2005-12-09

Applicant: INTEL CORP

Inventor： MA QING ,  LIN XINTIAN ,  BETTNER ALLEN

IPC: H01Q13/10

公开(公告)号：GB2447158A

公开(公告)日：2008-09-03

申请号：GB0807714

申请日：2006-12-06

Applicant: INTEL CORP

Inventor： RAO VALLURI ,  DOROS THEODORE G ,  MA QING ,  SESHAN KRISHNA ,  WANG LI-PENG

IPC: H03H9/02 ,  H03H3/04 ,  H03H9/17 ,  H03H9/58

Abstract: Multiple FBARs may be manufactured on a single wafer and later diced. Ideally, all devices formed in a wafer would have the same resonance frequency. However, due to manufacturing variances, the frequency response of the FBAR devices may vary slightly across the wafer. An RF map may be created to determine zones (50, 52) over the wafer where FBARs in that zone all vary from a target frequency by a similar degree. A tuning layer (40) may be deposited over the wafer. Lithographically patterned features to the tuning layer based on the zones identified by the RF map may be used to correct the FBARs to a target resonance frequency with the FBARs still intact on the wafer.

公开(公告)号：DE60318283D1

公开(公告)日：2008-02-07

申请号：DE60318283

申请日：2003-07-24

Applicant: INTEL CORP

Inventor： WANG LI-PENG ,  BAR-SADEH EYAL ,  RAO VALLURI ,  HECK JOHN ,  MA QING ,  TRAN QUAN ,  TALALYEVSKY ALEXANDER ,  GINSBURG EYAL

IPC: H03H3/02 ,  H03H9/24 ,  H03H9/205 ,  H03H9/54 ,  H03H9/56

Abstract: A film bulk acoustic resonator filter (10) may be formed with a plurality of interconnected series and shunt film bulk acoustic resonators (38) formed on the same membrane (35). Each of the film bulk acoustic resonators (38) may be formed from a common lower conductive layer which is defined to form the bottom electrode (32) of each film bulk acoustic resonator (38). A common top conductive layer may be defined to form each top electrode (36) of each film bulk acoustic resonator (38). A common piezoelectric film layer (34), that may or may not be patterned, forms a continuous or discontinuous film.

公开(公告)号：DE60317680D1

公开(公告)日：2008-01-03

申请号：DE60317680

申请日：2003-08-13

Applicant: INTEL CORP

Inventor： MA QING

IPC: B81B3/00 ,  H01H59/00

Abstract: A microelectromechanical system (MEMS) switch that includes a signal contact, an actuation electrode and a beam that engages the signal contact when a voltage is applied to the actuation electrode. The signal contact includes a first portion and a second portion. The actuation electrode is positioned between the first and second portions of the signal contact.