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    84.
    发明专利
    未知

    公开(公告)号：FR2842944A1

    公开(公告)日：2004-01-30

    申请号：FR0209347

    申请日：2002-07-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERREIRA PAUL ,  CORONEL PHILIPPE

    IPC: H01L21/033 ,  H01L21/311 ,  H01L21/60 ,  H01L23/50 ,  H01L21/265

    Abstract: The method for making contact openings in the upper surface of an integrated circuit in regions between higher zones applies in two cases, when the higher zones are well-spaced with noncritical openings (41), and when the higher zones are in proximity with critical openings (42). The method comprises the steps of covering the upper surface structure with a first protection layer (20); making the noncritical openings (41) in the first protection layer; covering the structure with the secodn protection layer; oblique irradiation carried out so that the second protection layer is not irradiated at the bottom of regions between two higher zones; eliminating the nonirradiated parts of the second protection layer; eliminating the parts of the first protection layer at locations where the second protection layer has been eliminated; and eliminating the irradiated parts of the second protection layer. The first protection layer (20) is of silicon nitride. The second protection layer is of polycrystalline silicon. The irradiation process is that of boron implanting. The oblique irradiation is carried out at an angle in the range 45-60 deg. The higher zones correspond to the gates (3) of MOS transistors. The zones susceptible of contact, that is a short-circuit, are covered with a metal silicide. The step of making the noncritical openings (41) comprises the steps of covering the structure with a planarization layer; eliminating the planarization layer at locations of the openings; etching the openings in the first protection layer; and eliminating the planarization layer. The planarization layer is of resin.

    Semiconductor device with enveloping gate encapsulated in an insulating medium
    85.
    发明专利
    Semiconductor device with enveloping gate encapsulated in an insulating medium 未知

    公开(公告)号：FR2838238A1

    公开(公告)日：2003-10-10

    申请号：FR0204358

    申请日：2002-04-08

    Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

    Inventor： CORONEL PHILIPPE ,  MONFRAY STEPHANE ,  SKOTNICKI THOMAS

    IPC: H01L21/336 ,  H01L29/786

    Abstract: The device comprises a semiconductor substrate (SB), a base insulator layer (BOX) formed on the substrate, a semiconductor channel region extending in longitudinal direction and enveloping the channel region. The regions of source (S), channel (CN) and drain (D) are formed in a continuous semiconductor layer (200) which is substantially flat and parallel to the upper surface of the substrate (SB), and the region of source, drain and gate (80) are encapsulated so to ensure an electrical insulation between the gate region and the regions of source and drain, and also between the substrate and the regions of source, drain, gate and channel. The thickness of the continuous semiconductor layer (200) is of the order of tens of nanometers. The gate region (80) is continuous, or formed of upper layer and lower parts separated by a dielectric layer. Independent claims are also included for: (1) an integrated circuit comprising the semiconductor device; and (2) a method for manufacturing the device comprising the formation of the base insulator layer, the formation of a silicon layer encapsulated between two layers, anisotropic etching, selective isotropic etching, filling tunnels with dielectric material, anisotropic etching, total selective etching of the remainders of encapsulation layers, oxidation of remainder of silicon layer, and filling spaces resulting from etching with the gate material.

    Integrated circuit with electromechanical component includes cavity defined between two substrates for auxiliary component
    86.
    发明专利
    Integrated circuit with electromechanical component includes cavity defined between two substrates for auxiliary component 未知

    公开(公告)号：FR2833106A1

    公开(公告)日：2003-06-06

    申请号：FR0115594

    申请日：2001-12-03

    Applicant: ST MICROELECTRONICS SA

    Inventor： FARCY ALEXIS ,  CORONEL PHILIPPE ,  ANCEY PASCAL ,  TORRES JOAQUIM

    IPC: B81B7/00 ,  B81C3/00 ,  H01L21/50 ,  H01L21/56 ,  B81C1/00

    Abstract: The circuit includes a first semiconductor substrate supporting the electronic circuit, and a second substrate carrying an electromechanical component. The two substrates are glued together forming a sealed and protective enclosure for the auxiliary component. The first phase of manufacture includes forming the semiconductor chip (PC) within a first substrate, and forming a cavity in the upper surface of this substrate to accommodate an auxiliary component. A wall remains around the cavity, leaving the cavity as a well. The second phase includes formation of the auxiliary component (CAX) on a second semiconductor substrate (SB2), separate from the first. The second substrate is then turned over and applied to the first substrate as a lid with the auxiliary component hanging within the cavity of the first substrate. The two substrates are glued together forming a sealed and protective enclosure for the auxiliary component.

    87.
    发明专利
    未知

    公开(公告)号：FR2819633B1

    公开(公告)日：2003-05-30

    申请号：FR0100691

    申请日：2001-01-18

    Applicant: ST MICROELECTRONICS SA

    Inventor： CORONEL PHILIPPE ,  PIAZZA MARC ,  LEVERD FRANCOIS

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: The invention relates to a DRAM integration method that does away with the alignment margins inherent to the photoetching step of the upper electrode of the capacitance for inserting the bit line contact. The removal of the upper electrode is self-aligned on the lower electrode of the capacitance. This is accomplished by forming a difference in topography at the point where the opening of the upper electrode is to be made, and depositing a non-doped polysilicon layer on the upper electrode. An implantation of dopants is performed on this layer, and the part of the non-doped layer located in the lower part of the zone showing the difference in topography is selectively etched. The remainder of the polysilicon layer and the part of the upper electrode located in the lower layer are also etched.

    89.
    发明专利
    未知

    公开(公告)号：FR2821208A1

    公开(公告)日：2002-08-23

    申请号：FR0102347

    申请日：2001-02-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： CORONEL PHILIPPE ,  LEVERD FRANCOIS ,  FERREIRA PAUL

    IPC: H01L21/60 ,  H01L21/768 ,  H01L23/52 ,  H01L21/8239

    Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

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