公开(公告)号：KR1020100083566A

公开(公告)日：2010-07-22

申请号：KR1020090003016

申请日：2009-01-14

Applicant: 삼성전자주식회사

Inventor： 김원주 ,  박윤동 ,  성정헌 ,  경용구 ,  최상무 ,  이태희

IPC: G11C16/24 ,  H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11578 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/0688

Abstract: PURPOSE: A non-volatile memory device having stack structure, memory card, and an electronic system are provided to simplify the wiring and layout of a core circuit unit and a bottom signal line. CONSTITUTION: A laminated NAND cell array(250) is formed on a substrate(210). The laminated NAND cell array comprises a NAND strings which are perpendicularly laminated on the substrate. A plurality of signal lines(230) are combined in the laminated NAND cell array. Signal lines are formed on the bottom of laminated NAND cell array or are formed on the substrate into which an insulating layer is inserted. The signal lines are electrically connected with the laminated NAND cell array. The laminated NAND cell array is connected to the signal lines through a plurality of perpendicular plugs(240).

Abstract translation: 目的：提供具有堆叠结构，存储卡和电子系统的非易失性存储器件，以简化核心电路单元和底部信号线的布线和布局。 构成：在衬底（210）上形成层压NAND单元阵列（250）。 层叠NAND单元阵列包括垂直层压在基板上的NAND串。 多个信号线（230）组合在层叠NAND单元阵列中。 信号线形成在层叠NAND单元阵列的底部，或者形成在其上插入有绝缘层的基板上。 信号线与层叠的NAND单元阵列电连接。 层叠NAND单元阵列通过多个垂直插头（240）连接到信号线。

公开(公告)号：KR1020090012583A

公开(公告)日：2009-02-04

申请号：KR1020070076523

申请日：2007-07-30

Applicant: 삼성전자주식회사

Inventor： 김영필 ,  김기홍 ,  김진범 ,  정인선 ,  경용구

IPC: H01L21/336

Abstract: A manufacturing method of a semiconductor integrated circuit device is provided to steadily fill up the recess with the semiconductor layer without generating the void in the recess. A manufacturing method of a semiconductor integrated circuit device comprises a step for forming the first insulating layer(110); a step for forming the semiconductor layer; a step for forming the second insulating layer; a step for partly removing the semiconductor layer, a step for removing the second insulating layer; a step for performing an optional epitaxial process(140) in the semiconductor layer. The first insulating layer includes the recess. The semiconductor layer covers the recess.

Abstract translation: 提供半导体集成电路器件的制造方法，以在半导体层内稳定地填充凹槽而不会在凹部中产生空隙。 半导体集成电路器件的制造方法包括形成第一绝缘层（110）的步骤。 形成半导体层的步骤; 形成第二绝缘层的步骤; 用于部分去除半导体层的步骤，去除第二绝缘层的步骤; 在半导体层中执行可选的外延工艺（140）的步骤。 第一绝缘层包括凹部。 半导体层覆盖凹部。

公开(公告)号：KR1020160051152A

公开(公告)日：2016-05-11

申请号：KR1020140150623

申请日：2014-10-31

Applicant: 삼성전자주식회사

Inventor： 심저영 ,  전우성 ,  경용구 ,  문의성

IPC: C09J5/02 ,  B81B3/00

CPC classification number: B01L3/502707 ,  B01L2200/0689 ,  B01L2300/0887 ,  B01L2300/12 ,  B29C65/02 ,  B29C66/026 ,  B29C66/028 ,  B29C66/112 ,  B29C66/1122 ,  B29C66/114 ,  B29C66/5412 ,  B29C66/71 ,  B29L2031/7506 ,  B29L2031/756 ,  B81C3/001 ,  B29K2025/06 ,  B29K2083/00 ,  B29K2023/00 ,  B29K2027/08 ,  B29K2027/18 ,  B29K2033/08 ,  B29K2033/12 ,  B29K2067/003 ,  B29K2069/00

Abstract: 폴리실록산이접촉된플라스틱표면에질소또는암모니아플라즈마를제공하는단계를포함하는, 2개표면을결합시키는방법및 그에의하여제조된구조체를제공한다.

Abstract translation: 提供了一种有效地粘合两个表面的方法，其包括在塑料接触聚硅氧烷的表面上提供氮或氨等离子体的步骤。 还提供了由此产生的结构。

公开(公告)号：KR1020100100550A

公开(公告)日：2010-09-15

申请号：KR1020090025989

申请日：2009-03-26

Applicant: 삼성전자주식회사

Inventor： 유동철 ,  이은하 ,  이형익 ,  황기현 ,  허성 ,  최한메 ,  경용구 ,  김병주

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/02145 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28282 ,  H01L21/3141 ,  H01L27/11521 ,  H01L21/28273

Abstract: PURPOSE: A method for manufacturing a memory device is provided to prevent the leakage current of a blocking dielectric film by suppressing the interfacial reaction of an silicon oxide in a first dielectric film and an aluminum oxide in a third dielectric film. CONSTITUTION: A tunnel dielectric film(110) is formed on a substrate(10). An electric charge trapping film(120) is formed on the tunnel dielectric film. A blocking dielectric film(130) is formed on the electric charge trapping film. A first dielectric film(131) including a silicon oxide is formed on the electric charge trapping film. A second dielectric film(133) including an aluminum silicate is formed on the first dielectric film. A third dielectric layer(135) including an aluminum oxide is formed on the second dielectric film.

Abstract translation: 目的：提供一种用于制造存储器件的方法，通过抑制第三绝缘膜中的第一电介质膜和氧化铝中的氧化硅的界面反应来防止阻挡电介质膜的漏电流。 构成：在衬底（10）上形成隧道电介质膜（110）。 在隧道电介质膜上形成电荷捕获膜（120）。 在电荷捕获膜上形成阻挡电介质膜（130）。 在电荷捕获膜上形成包括氧化硅的第一电介质膜（131）。 在第一电介质膜上形成包括硅酸铝的第二电介质膜（133）。 在第二电介质膜上形成包括氧化铝的第三电介质层（135）。