中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.021 seconds)

    Connector applied underfill
    1.
    发明公开
    Connector applied underfill 审中-公开
    连接器应用底部填充

    公开(公告)号：EP1951013A2

    公开(公告)日：2008-07-30

    申请号：EP08100444.2

    申请日：2008-01-14

    Applicant: Delphi Technologies, Inc.

    Inventor： Brandenburg, Scott D. ,  Delheimer, Charles I.

    IPC: H05K3/30 ,  H05K3/34

    CPC classification number: H05K3/305 ,  H01R12/7041 ,  H01R43/00 ,  H05K3/3426 ,  H05K3/3436 ,  H05K2201/0129 ,  H05K2201/10977 ,  H05K2201/10984 ,  H05K2203/041 ,  H05K2203/1105 ,  Y02P70/613

    Abstract: Processes for reliably and durably mounting a connector body to a surface of a circuit board without using conventional underfill and overmolding techniques are provided. These processes involve preparation of a self adhering connector subassembly (30) comprising a connector body (12) and an activatable solid adhesive (24) disposed on a mounting surface (32) of the connector body (12), positioning of the subassembly (30) on a circuit board, and activation of the adhesive (24) to securely attach the connector body (12) to the circuit board. The activable solid adhesive (24) has a pattern of openings in which the solder balls (18) project.

    Abstract translation: 提供了在不使用传统底部填充和包覆成型技术的情况下可靠且持久地将连接器主体安装到电路板表面的工艺。 这些过程涉及制备包括连接器本体（12）和设置在连接器本体（12）的安装表面（32）上的可激活固体粘合剂（24）的自粘合连接器子组件（30），定位子组件 ）放置在电路板上，并且激活粘合剂（24）以将连接器主体（12）牢固地连接到电路板。 可活化的固体粘合剂（24）具有其中焊球（18）突出的开口图案。

    Method of mounting a leadless package and structure therefor
    3.
    发明公开
    Method of mounting a leadless package and structure therefor 审中-公开
    Verfahren zum Montieren eines drahtlosenGehäusesund Strukturdafür

    公开(公告)号：EP1377144A2

    公开(公告)日：2004-01-02

    申请号：EP03076653.9

    申请日：2003-05-28

    Applicant: Delphi Technologies, Inc.

    Inventor： Delheimer, Charles I.

    IPC: H05K3/34 ,  G06F1/20

    CPC classification number: H01L23/498 ,  H01L23/3677 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0206 ,  H05K3/0094 ,  H05K3/341 ,  H05K3/3452 ,  H05K3/42 ,  H05K2201/099 ,  H05K2201/10727 ,  H05K2201/10969 ,  H05K2203/0455 ,  H05K2203/1178 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A method and circuit structure (10) for mounting a leadless IC package (30) to a substrate (12) having a thermal pad (14) on a first surface thereof, a plurality of contact pads (16) surrounding the thermal pad (14), and one or more plated vias (18) in the thermal pad (14). The leadless package (30) is attached to the substrate (12) with solder (36) that thermally connects the package (30) to the thermal pad (14). To prevent solder flow into the plated vias (18) during reflow, a solder mask (20,21,22) is provided on the first surface of the substrate (12), at least a portion (21) of which is deposited on the thermal pad (14) and surrounds the plated vias (18) but does not block the plated vias (18). The solder mask portion (21) defines a barrier between the solder (36) and the plated vias (18), but allows for outgassing through the vias (18) during solder reflow.

    Abstract translation: 一种用于将无铅IC封装（30）安装到其第一表面上具有热垫（14）的衬底（12）的方法和电路结构（10），围绕所述散热垫（14）的多个接触焊盘 ）和一个或多个电镀通孔（18）在散热焊盘（14）中。 无引线封装（30）通过将封装（30）热连接到散热焊盘（14）的焊料（36）附接到基板（12）。 为了防止在回流期间焊料流入镀覆通孔（18）中，在衬底（12）的第一表面上提供焊料掩模（20,21,22），其中至少一部分（21）沉积在衬底 热垫（14）并且围绕镀覆的通孔（18），但不阻挡镀覆的通孔（18）。 焊接掩模部分（21）限定焊料（36）和镀覆通孔（18）之间的阻挡层，但是允许在回流焊时通过通孔（18）而脱气。

    Electronic assembly with a noflow underfill
    4.
    发明公开
    Electronic assembly with a noflow underfill 审中-公开
    Elektronische Baugruppe mit no-flow-Unterfüllung

    公开(公告)号：EP1710832A2

    公开(公告)日：2006-10-11

    申请号：EP06075745.7

    申请日：2006-03-30

    Applicant: Delphi Technologies, Inc.

    Inventor： Delheimer, Charles I. ,  Chaudhuri, Arun K. ,  Stepniak, Frank

    IPC: H01L21/56 ,  H01L23/485

    CPC classification number: H01L24/10 ,  H01L21/563 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/73203 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/0401

    Abstract: An electronic assembly (400) includes an integrated circuit (IC) die (306), a substrate (302) and a no-flow underfill (310) applied between the IC die (306) and the substrate (302). The IC die (306) includes a plurality of conductive contacts formed on a surface of the die (306). The substrate (302) includes a plurality of conductive traces (304) formed on a surface of the substrate (302) and electrically connected to at least one of the conductive contacts by electrical interconnects (320). The interconnects (320) each include a polymer core having an electrically conductive solderable outer surface. The polymer core has a coefficient of thermal expansion (CTE) that approximately matches the CTE of the no-flow underfill (310).

    Abstract translation: 电子组件（400）包括施加在IC管芯（306）和衬底（302）之间的集成电路（IC）管芯（306），衬底（302）和不流动底部填充物（310）。 IC芯片（306）包括形成在模具（306）的表面上的多个导电触点。 衬底（302）包括形成在衬底（302）的表面上并通过电互连（320）电连接到至少一个导电触点的多个导电迹线（304）。 互连（320）各自包括具有导电可焊接外表面的聚合物芯。 聚合物芯具有与无流动底部填充物（310）的CTE近似匹配的热膨胀系数（CTE）。

    Interconnect for an electrical circuit substrate
    10.
    发明公开
    Interconnect for an electrical circuit substrate 审中-公开
    Verbindungfüreine elektrisches Schaltsubstrat

    公开(公告)号：EP1968362A2

    公开(公告)日：2008-09-10

    申请号：EP08151809.4

    申请日：2008-02-22

    Applicant: Delphi Technologies, Inc.

    Inventor： Burns, Jeffrey H. ,  Delheimer, Charles I.

    IPC: H05K1/14

    CPC classification number: H05K1/145 ,  H05K1/023 ,  H05K1/0274 ,  H05K1/141 ,  H05K3/303 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/09072 ,  H05K2201/10121 ,  H05K2201/10636 ,  H05K2201/10727 ,  H05K2201/10734 ,  H05K2201/2036 ,  Y02P70/611

    Abstract: A passive surface mount part (30,32,44) such as a capacitor or a resistor is employed to attach a first substrate (10) to a second substrate (12), or a semiconductor device (18) to a substrate (12), for an electrical circuit assembly. Applicable forms of substrates (10,12) include a printed circuit board such as a motherboard and a daughterboard, and applicable forms of semiconductor devices (18) include an integrated circuit. In an aspect, a low profile attachment is provided forming a planar structure. Space is conserved, signal transmission is provided, and electrical performance is increased. In another aspect, a standoff is defined between the substrates (10,12) setting the substrates apart a desired distance, compensating for any surface irregularities, increasing thermal separation, and increasing interconnect flexibility. As an application, the standoff defined between the substrates (10,12) can be utilized for a structure such as optical glass structure (28) to be situated between the substrates for use with an optical circuit assembly (26).

    Abstract translation: 使用诸如电容器或电阻器的无源表面安装部件（30,32,44）将第一基板（10）附接到第二基板（12）或将半导体器件（18）附接到基板（12） ，用于电路组件。 衬底（10,12）的适用形式包括诸如母板和子板的印刷电路板，并且半导体器件（18）的适用形式包括集成电路。 在一方面，提供形成平面结构的低轮廓附件。 节省空间，提供信号传输，并提高电气性能。 在另一方面，在衬底（10,12）之间限定了将衬底间隔开所需距离，补偿任何表面凹凸，增加热分离和增加互连柔性的间隙。 作为应用，限定在基板（10,12）之间的间隔可用于诸如光学玻璃结构（28）之类的结构，位于基板之间以用于光学电路组件（26）。

Patent Agency Ranking