公开(公告)号：EP1703557A3

公开(公告)日：2009-08-19

申请号：EP06075528.7

申请日：2006-03-07

Applicant: Delphi Technologies, Inc.

Inventor： Chengalva, Suresh K. ,  Myers, Bruce A. ,  Walsh, Matthew R.

IPC: H01L23/427 ,  H01L23/373 ,  H01L23/367 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L23/3675 ,  H01L23/4275 ,  H01L23/433 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic assembly (100) with integral thermal transient suppression includes an integrated circuit (IC) chip (106) disposed within a cavity (103) of an IC device package (102). A transient thermal suppression material (TTSM) (110) is disposed in the cavity (103) in thermal contact with the IC chip (106). A heat sink (112) may also be provided in thermal contact with the chip (106). When present, the heat sink (112) serves as a cover of the packaged IC chip (106) and may include fins (112A,112B) extending from an upper surface (in contact with air) and a lower surface (in thermal contact with the TTSM (110)).The TTSM (110) may be thought of as a phase change material that absorbs energy dissipated by the IC chip (106) in a phase change event.

公开(公告)号：EP1740027A3

公开(公告)日：2009-06-03

申请号：EP06076193.9

申请日：2006-06-08

Applicant: Delphi Technologies, Inc.

Inventor： Brandenburg, Scott D. ,  Laudick, David A. ,  Degenkolb, Thomas A. ,  Walsh, Matthew R. ,  Tsai, Jeenhuei S.

IPC: H05K3/28

CPC classification number: H01L23/4334 ,  B29C45/14065 ,  B29C45/14467 ,  B29C45/14655 ,  H01L23/3121 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K3/0061 ,  H05K3/284 ,  H05K2201/10189 ,  H05K2201/1056 ,  H05K2201/10674 ,  H05K2203/1316 ,  H01L2924/00

Abstract: A technique for manufacturing an electronic assembly uses a mold (40) that has a first mold portion (44) and a second mold portion (42). The first mold portion (44) includes a plurality of spaced mold pins (46) extending from an inner surface. A cavity of the first and second mold portions (44,42) provides a mold cavity (111), when joined. A backplate (110) is also provided that includes a plurality of support pedestals (112) and an integrated heatsink (114) extending from a first side of the backplate (110). A substrate (102) includes a first side of an integrated circuit (IC) die (106A) mounted to a first side of the substrate (102). The backplate (110) and the substrate (102) are placed within the cavity of the second mold portion and the support pedestals (112) are in contact with the first side of the substrate (102). The first and second mold portions (44,42) are joined and the mold pins (46) contact a second surface of the substrate (102) during an overmolding process.

公开(公告)号：EP2031692A1

公开(公告)日：2009-03-04

申请号：EP08169722.9

申请日：2007-03-13

Applicant: Delphi Technologies, Inc.

Inventor： Berlin, Carl W. ,  Nair, Deepukumar M. ,  Walsh, Matthew R.

IPC: H01P1/203

CPC classification number: H01P1/203 ,  H01P1/2005 ,  H05K1/0233 ,  H05K1/0236 ,  H05K3/4069 ,  H05K2201/0215 ,  H05K2201/086 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2203/0557 ,  H05K2203/104 ,  H05K2203/171

Abstract: Tuned Electromagnetic Bandgap (EBG)devices (10, 30), and a method for making and tuning tuned EBG devices (10, 30) are provided. The method includes the steps of providing first and second overlapping substrates (32, 32a), placing magnetically alignable conductive material (36) between the substrates (32, 32a), and applying a magnetic field (44, 45) in the vicinity of the magnetically alignable conductive material (36) to align at least some of the material into conductive vias (46, 47). The method further includes the steps of physically altering via characteristics of EBG devices (10, 30) to tune the bandpass and resonant frequencies of the EBG devices (10, 30).

公开(公告)号：EP1530234A3

公开(公告)日：2011-11-02

申请号：EP04077976.1

申请日：2004-10-29

Applicant: Delphi Technologies, Inc.

Inventor： Brandenburg, Scott D. ,  Oman, Todd P. ,  Walsh, Matthew R.

IPC: H01L23/36

CPC classification number: H01L23/5387 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L25/072 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15747 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A heat sinkable package that includes a power device package (200, 300, 400, 500) including an active side (A) and a non-active side (N) is disclosed. The non-active side (N) includes a heat sinkable surface positioned adjacent to a product case (C). Another embodiment of the invention is directed to a method for manufacturing a heat sinkable package. The method comprises the steps of placing at least one flip chip (204, 304) over a flexible circuit (208) within a mold tool; compensating for height variances of the flip chips (204, 204); and positioning an input/output on an active side (A) of the power device package (200, 300, 400, 500) opposite a non-active side (N) of the power device package.

公开(公告)号：EP2043150A2

公开(公告)日：2009-04-01

申请号：EP08164601.0

申请日：2008-09-18

Applicant: Delphi Technologies, Inc.

Inventor： Walsh, Matthew R. ,  Nair, Deepukumar M. ,  Zimmerman, David W. ,  Haffke, Benjamen E. ,  Brandenburg, Scott D.

IPC: H01L23/66

CPC classification number: H01L23/66 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2223/6677 ,  H01L2924/1617 ,  H01L2924/19032 ,  H01L2924/19039 ,  H01P5/107

Abstract: A microwave communication package (10) is constructed on an electrically conducting base plate (12) having a first side (14) defining a base plate cavity (16), with an antenna apparatus (40) mounted on an opposite, second side (18). A dielectric substrate (20) on the first side of the base plate covers the base plate cavity; and sealing apparatus (72) contacting the dielectric substrate and the base plate completely around the base plate cavity hermetically seals the cavity. Circuitry (30, 32) mounted on a surface of the substrate within the base plate cavity includes one or more microstrip lines (54) communicating components (30) to one or more waveguides comprising openings (50) extending through the base plate; and the waveguides are coupled at their opposite ends to the antenna apparatus.

Abstract translation: 微波通信封装（10）构造在具有限定基板腔（16）的第一侧面（14）的导电基板（12）上，天线装置（40）安装在相对的第二侧（18 ）。 基板的第一侧上的电介质基板（20）覆盖基板空腔; 并且密封装置（72）使绝缘基片和基板完全围绕底板腔体密封，密封空腔。 安装在基板腔内的基板表面上的电路（30,32）包括一个或多个微带线路（54），其将部件（30）连接到一个或多个包括延伸穿过基板的开口（50）的波导; 并且波导在其相对端耦合到天线装置。

公开(公告)号：EP1628509A2

公开(公告)日：2006-02-22

申请号：EP05076727.6

申请日：2005-07-27

Applicant: Delphi Technologies, Inc.

Inventor： Delheimer, Charles I. ,  Workman, Derek B. ,  Tsai, Jeenhuei S. ,  Walsh, Matthew R. ,  Brandenburg, Scott D. ,  Thompson, Brian D.

IPC: H05K3/28 ,  H05K3/30

CPC classification number: H05K3/303 ,  H01L21/563 ,  H01L23/3121 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1433 ,  H01L2924/19041 ,  H05K3/284 ,  H05K2201/10674 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic module (100) includes a substrate (108), at least one surface mounted integrated circuit (IC) component (110) and an underfill material (122). The substrate (108) includes a plurality of electrically conductive traces (118A,118B), formed on at least one surface of the substrate (108), and the component (110) is electrically coupled to at least one of the conductive traces (118A,118B). The underfill material (122) is positioned between the component (110) and the substrate (108) and provides at least one pedestal that supports the component (110) during encapsulation. The underfill material (122), when cured, maintains the integrity of the electrical connections between the component (110) and the conductive traces (118A,118B).

Abstract translation: 电子模块（100）包括衬底（108），至少一个表面安装集成电路（IC）部件（110）和底部填充材料（122）。 衬底（108）包括形成在衬底（108）的至少一个表面上的多个导电迹线（118A，118B），并且部件（110）电耦合到导电迹线（118A）中的至少一个 ，118B）。 底部填充材料（122）位于部件（110）和基板（108）之间，并且提供至少一个在封装期间支撑部件（110）的基座。 底部填充材料（122）在固化时保持部件（110）和导电迹线（118A，118B）之间的电连接的完整性。

公开(公告)号：EP1740027B1

公开(公告)日：2019-01-23

申请号：EP06076193.9

申请日：2006-06-08

Applicant: Delphi Technologies, Inc.

Inventor： Brandenburg, Scott D. ,  Laudick, David A. ,  Degenkolb, Thomas A. ,  Walsh, Matthew R. ,  Tsai, Jeenhuei S.

IPC: H05K3/28

公开(公告)号：EP1837945A1

公开(公告)日：2007-09-26

申请号：EP07075186.2

申请日：2007-03-13

Applicant: Delphi Technologies, Inc.

Inventor： Berlin, Carl W. ,  Nair, Deepukumar M. ,  Walsh, Matthew R.

IPC: H01P1/203

CPC classification number: H01P1/203 ,  H01P1/2005 ,  H05K1/0233 ,  H05K1/0236 ,  H05K3/4069 ,  H05K2201/0215 ,  H05K2201/086 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2203/0557 ,  H05K2203/104 ,  H05K2203/171

Abstract: Tuned Electromagnetic Bandgap (EBG)devices (10, 30), and a method for making and tuning tuned EBG devices (10, 30) are provided. The method includes the steps of providing first and second overlapping substrates (32, 32a), placing magnetically alignable conductive material (36) between the substrates (32, 32a), and applying a magnetic field (44, 45) in the vicinity of the magnetically alignable conductive material (36) to align at least some of the material into conductive vias (46, 47). The method further includes the steps of physically altering via characteristics of EBG devices (10, 30) to tune the bandpass and resonant frequencies of the EBG devices (10, 30).

Abstract translation: 提供调谐电磁带隙（EBG）装置（10，30），以及用于制备和调谐调谐EBG装置（10，30）的方法。 该方法包括提供第一和第二重叠衬底（32，32A）的步骤，放置磁性对准基板之间能够导电材料（36）（32，32A），和施加磁场（44,45）中的附近 磁性对准能够导电材料（36）以对齐的至少一些的材料的成导电通孔（46，47）。 该方法包括经由EBG设备的特性的进一步的物理改变的步骤（10，30）来调谐带通和EBG装置的共振频率（10，30）。

公开(公告)号：EP1748518A2

公开(公告)日：2007-01-31

申请号：EP06076297.8

申请日：2006-06-26

Applicant: Delphi Technologies, Inc.

Inventor： Brandeburg, Scott D. ,  Degenkolb, Thomas A. ,  Walsh, Matthew R.

IPC: H01R12/04

CPC classification number: H01R43/0256 ,  H01R12/716 ,  H01R43/0249

Abstract: A surface mount connector (11) and assembly including the surface mount connector (10) is shown and described. The assembly comprises a substrate (13) and a connector (11) including a carrier (14), and at least one electrical connecting element (16) having first (22) and second ends (24), wherein at least a portion of the first end (22) extends through the carrier (14) to electrically adjoin and physically secure the connector (11) to the substrate (13). A reinforcement medium (36) is disposed about at least a portion of surface mount connector (11) and said substrate (13).

Abstract translation: 示出并描述了表面安装连接器（11）和包括表面安装连接器（10）的组件。 所述组件包括基板（13）和包括载体（14）的连接器（11）以及具有第一端（22）和第二端（24）的至少一个电连接元件（16），其中至少一部分 第一端（22）延伸穿过载体（14）以将连接器（11）物理地固定到基板（13）上。 加强介质（36）围绕表面安装连接器（11）和所述基板（13）的至少一部分设置。

公开(公告)号：EP1628509A3

公开(公告)日：2006-10-04

申请号：EP05076727.6

申请日：2005-07-27

Applicant: Delphi Technologies, Inc.

Inventor： Delheimer, Charles I. ,  Workman, Derek B. ,  Tsai, Jeenhuei S. ,  Walsh, Matthew R. ,  Brandenburg, Scott D. ,  Thompson, Brian D.

IPC: H05K3/28 ,  H05K3/30 ,  H01L23/31 ,  H01L21/56

CPC classification number: H05K3/303 ,  H01L21/563 ,  H01L23/3121 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1433 ,  H01L2924/19041 ,  H05K3/284 ,  H05K2201/10674 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic module (100) includes a substrate (108), at least one surface mounted integrated circuit (IC) component (110) and an underfill material (122). The substrate (108) includes a plurality of electrically conductive traces (118A,118B), formed on at least one surface of the substrate (108), and the component (110) is electrically coupled to at least one of the conductive traces (118A,118B). The underfill material (122) is positioned between the component (110) and the substrate (108) and provides at least one pedestal that supports the component (110) during encapsulation. The underfill material (122), when cured, maintains the integrity of the electrical connections between the component (110) and the conductive traces (118A,118B).