公开(公告)号：JPH11274158A

公开(公告)日：1999-10-08

申请号：JP4899

申请日：1999-01-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： ARNDT KENNETH C ,  CONTI RICHARD A ,  DOBUZINSKY DAVID M ,  ECONOMIKOS LAERTIS ,  GAMBINO JEFFREY P ,  HOH PETER D ,  NARAYAN CHANDRASEKHAR

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

Abstract: PROBLEM TO BE SOLVED: To check cracks within a final passivation laver 13 of an integrated circuit by reducing the stresses within a peripheral dielectric which are due to acute corner of a circuit pattern.
SOLUTION: Stresses generally induced inside a dielectric is reduced by formings 15 and 17, at lower corner 14" of a circuit pattern 11 before adhering an outer layer (that is, a passivation layer) 13. When patterning it by metallic RIE process, this kind of rounding of the corner is achieved by a two-step metallic etching process, including the first step of creating a vertical sidewall and the second step of tapering the lower part of the vertical sidewall or creating a tapered spacer 15 along the under section of the vertical sidewall. When patterning it by a die machine process, this kind of rounding of the corner is achieved by a two-step trench etching process, including a first step of creating a vertical sidewall and a second step of creating a tapered side wall along the under section of the vertical sidewall.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：通过减少外围电介质中由于电路图案的急剧拐角引起的应力来检查集成电路的最终钝化层13内的裂纹。 解决方案：在粘附外层（即钝化层）13之前的电路图案11的下角14“处，通过结构15和17减小电介质内部的应力。当通过金属RIE工艺对其进行图案化时， 通过两步金属蚀刻工艺实现角部的圆角化，包括形成垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤或者沿着垂直侧壁的下部形成锥形间隔件15 垂直侧壁，当通过模具机加工对其进行图案化时，通过两步沟槽蚀刻工艺实现角部圆化，包括形成垂直侧壁的第一步骤和产生锥形侧壁的第二步骤 沿着垂直侧壁的下部。

公开(公告)号：WO03019619A3

公开(公告)日：2003-10-16

申请号：PCT/US0225507

申请日：2002-08-08

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： CONTI RICHARD A ,  EDELSTEIN DANIEL ,  LEE GILL YONG

IPC: H01L21/768 ,  C23C16/40 ,  H01L21/312 ,  H01L21/316 ,  H01L23/522 ,  H01L21/02

CPC classification number: H01L21/31604 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/3122 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/31633 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low-k pre-metal dielectric (PMD) structure on a semiconductor wafer and a method for making the PMD structure is described. The PMD structure includes a low-k dielectric film (170) that has good gap-filling characteristics, particularly where the gap (160) formed between features (130), such as gate stacks, has an aspect ratio greater than about 3. The method for forming the PMD structure uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precursor (260) such as TMCTS or OMCTS, an ozone-containing gas (270), and a source of dopants (280) for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film (170). Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combination thereof.

Abstract translation: 描述半导体晶片上的低k金属前介电（PMD）结构和制造PMD结构的方法。 PMD结构包括具有良好间隙填充特性的低k介电膜（170），特别是在特征（130）之间形成的间隙（160）（例如栅极堆叠）具有大于约3的纵横比时。 用于形成PMD结构的方法使用包括诸如TMCTS或OMCTS的含碳有机金属前体（260），含臭氧气体（270）和用于吸杂的掺杂剂源（280）的热亚低气压CVD工艺 碱性元素并降低电介质的回流温度，同时获得电介质膜（170）的期望的低k和间隙填充性能。 磷是吸收碱金属元素如钠的优选掺杂剂。 用于降低回流温度的附加掺杂剂包括但不限于硼，锗，砷，氟或其组合。

公开(公告)号：JP2000311948A

公开(公告)日：2000-11-07

申请号：JP2000092149

申请日：2000-03-29

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ARNDT KENNETH C ,  BRINTZINGER AXEL C ,  CONTI RICHARD A ,  COTE DONNA R ,  NARAYAN CHANDRASEKHAR ,  RAMACHANDRAN RAVIKUMAR ,  RUPP THOMAS S ,  SENTEIRU K SURIINIVUASAN

IPC: H01L21/82 ,  H01H69/02 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for generating a void fuse structure on a gate conductor stack. SOLUTION: A semiconductor substrate is provided, wherein a gate conductor stack 32 is provided on a shallow trench isolation region. Oxide layers 33 and 34 are formed on a substrate around the gate conductor stack 32, and an electric contact opening part etched to the substrate down to the oxide layer is filled with a first conductive material 40, establishing electric contact to the gate conductor stack. A conductive layer 41 of a second conductive material is allowed to stick to the oxide layer and the electric contact, and the oxide layer is anisotropically etched so that at least one etching hole, as far as the shallow trench isolation region through the oxide layer, is formed. A part 60 around the least the etching hole of the oxide layer is isotropically etched to form a void under at least a part of a conductive player pattern. The gate conductor stack comprises a fuse.

公开(公告)号：JPH10294291A

公开(公告)日：1998-11-04

申请号：JP31238297

申请日：1997-11-13

Applicant: IBM

Inventor： BRODSKY STEPHEN BRUCE ,  CONTI RICHARD A ,  SUBBANNA SESHADRI

IPC: C23C16/04 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To prevent deep quenching/encroachment into a silicon region, insufficient attachment, uncontrolled selectivity and irregular structure by reacting fire-resistant halogenide with an exposed surface of a silicon substrate and then reacting it with silicon containing gas and reacting it with hydrogen. SOLUTION: A preliminary adjusted wafer 10 is arranged on a heater base 22 with an electric field through 11 in a fire-resistant gas CVD reactor 20. Gas is supplied from gas supply sources 26, 28, 30, 32, 34 to a shower head 24 and gas 40 is also supplied to a rear. Here, fire-resistant metallic halogenide is reacted with a silicon substrate exposed surface in the existence of inert gas and fire-resistant metal is selectively attached to a silicon substrate exposed surface. Then, fire-resistant metallic halogenide is reacted with silicon containing gas, silicon substrate quenching is limited by fire-resistant metallic halogenide and a thickness of fire-resistant meal is increased. Furthermore, fire-resistant metallic halogenide is reacted with hydrogen and fire-resistant metal is further deposited.

公开(公告)号：WO2012099928A2

公开(公告)日：2012-07-26

申请号：PCT/US2012021664

申请日：2012-01-18

Applicant: IBM ,  AQUILINO MICHAEL V ,  BAIOCCO CHRISTOPHER V ,  CONTI RICHARD A ,  JAEGER DANIEL J ,  NARAYANAN VIJAY

Inventor： AQUILINO MICHAEL V ,  BAIOCCO CHRISTOPHER V ,  CONTI RICHARD A ,  JAEGER DANIEL J ,  NARAYANAN VIJAY

IPC: H01L21/762 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L29/517

Abstract: A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.

Abstract translation: 提供衬底。 STI沟槽形成在衬底中。 填充材料形成在STI沟槽中，然后平坦化。 衬底暴露于氧化环境中，在STI沟槽的底部和侧壁处生长衬垫。 衬垫可降低高k金属栅极器件中的Vt-W效应。

公开(公告)号：WO0245134A3

公开(公告)日：2003-04-03

申请号：PCT/US0151214

申请日：2001-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HORN PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/60 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

Abstract translation: 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

公开(公告)号：DE60133214D1

公开(公告)日：2008-04-24

申请号：DE60133214

申请日：2001-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HOH PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/8242 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8239

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

公开(公告)号：DE60133214T2

公开(公告)日：2009-04-23

申请号：DE60133214

申请日：2001-11-13

Applicant: IBM ,  QIMONDA AG

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HOH PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/8242 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8239

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

公开(公告)号：DE10236430A1

公开(公告)日：2003-02-27

申请号：DE10236430

申请日：2002-08-08

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CONTI RICHARD A ,  EDELSTEIN DANIEL C ,  LEE GILL YOUNG

IPC: C23C16/40 ,  H01L21/768 ,  H01L21/312 ,  H01L21/316 ,  H01L23/522

Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

公开(公告)号：MY134065A

公开(公告)日：2007-11-30

申请号：MYPI20022744

申请日：2002-07-19

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： CONTI RICHARD A ,  EDELSTEIN DANIEL C ,  LEE GILL Y

IPC: H01L21/31 ,  C23C16/40 ,  H01L21/768 ,  H01L21/312 ,  H01L21/316 ,  H01L23/522

Abstract: A METHOD IS DESCRIBED FOR FORMING A LOW-K DIELECTRIC FILM, IN PARTICULAR, A PRE-METAL DIELECTRIC (PMD) ON A SEMICONDUCTOR WAFER WHICH HAS GOOD GAP-FILLING CHARACTERISTICS. THE METHOD USES A THERMAL SUB-ATMOSPHERIC CVD PROCESS THAT INCLUDES A CARBON-CONTAINING ORGANOMETALLIC PRECUSOR SUCH AS TMCTS OR OMCTS, AN OZONE-CONTAINING GAS, AND A SOURCE OF DOPANTS FOR GETTERING ALKALI ELEMENTS AND FOR LOWERING THE REFLOW TEMPERATURE OF THE DIELECTRIC WHILE ATTAINING THE DESIRED LOW-K AND GAPFILLING PROPERTIES OF THE DIELECTRIC FILM. PHOSPHOROUS IS A PREFERRED DOPANT FOR GETTERING ALKALI ELEMENT SUCH AS SODIUM. ADDITIONAL DOPANTS FOR LOWERING THE REFLOW TEMPERATURE INCLUDE, BUT ARE NOT LIMITED TO BORON, GERMANIUM, ARSENIC, FLUORINE OR COMBINATIONS THEREOF.(FIG 3)