公开(公告)号：EP2235744A4

公开(公告)日：2011-12-14

申请号：EP09704513

申请日：2009-01-15

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DORIS BRUCE B ,  HUANG ELBERT E ,  PURUSHOTHAMAN SAMPATH ,  RADENS CARL J

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

公开(公告)号：EP1620877A4

公开(公告)日：2009-12-09

申请号：EP04749753

申请日：2004-04-05

Applicant: IBM

Inventor： HEDRICK JEFFREY C ,  HUANG ELBERT E

IPC: H01L21/312 ,  H01L20060101 ,  H01L21/28 ,  H01L21/314 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76832 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3121 ,  H01L21/314 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures having low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer are described herein. The multilayered dielectric diffusion barrier layer are diffusion barriers to metal and barriers to air permeation. Methods and compositions relating to the generation of the structures are also described. The advantages of utilizing these low-k multilayered dielectric diffusion barrier layer is a gain in chip performance through a reduction in capacitance between conducting metal features and an increase in reliability as the multilayered dielectric diffusion barrier layer are impermeable to air and prevent metal diffusion.

公开(公告)号：EP1595276A4

公开(公告)日：2012-03-28

申请号：EP04705307

申请日：2004-01-26

Applicant: IBM

Inventor： GATES STEPHEN M ,  HEDRICK JEFFREY C ,  HUANG ELBERT E ,  PFEIFFER DIRK

IPC: G03G13/06 ,  H01L20060101 ,  H01L21/00 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/44 ,  H01L23/48 ,  H05B6/64

CPC classification number: H01L21/02126 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3125 ,  H01L21/316 ,  Y10S430/146 ,  Y10T428/31663

公开(公告)号：EP1595275A4

公开(公告)日：2007-10-31

申请号：EP04705302

申请日：2004-01-26

Applicant: IBM

Inventor： COHEN STEPHEN A ,  GATES STEPHAN M ,  HEDRICK JEFFREY C ,  HUANG ELBERT E ,  PFEIFFER DIRK

IPC: H01L23/532 ,  H01L20060101 ,  H01L21/00 ,  H01L21/312 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/02282 ,  H01L21/02126 ,  H01L21/02222 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3125 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31663 ,  H01L2924/00

Abstract: The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween where the ceramic diffusion barrier has a composition, SivNwCxOyHz, where 0.1≤v≤0.9, 0≤w≤0.5, 0.01≤x≤0.9, 0≤y≤0.7, 0.01≤z≤0.8 for v+w+x+y+Z=1. The ceramic diffusion barrier acts as a diffusion barrier to metals, i.e., copper. The present invention also comprises a method for forming the inventive ceramic diffusion barrier including the steps depositing a polymeric preceramic having a composition SivNwCxOyHz, where 0.1

公开(公告)号：JP2005217420A

公开(公告)日：2005-08-11

申请号：JP2005021358

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  COLBURN MATTHEW E ,  COONEY EDWARD C III ,  DALTON TIMOTHY J ,  FITZSIMMONS JOHN A ,  GAMBINO JEFFREY P ,  HUANG ELBERT E ,  LANE MICHAEL W ,  MCGAHAY VINCENT J ,  NICHOLSON LEE M ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SANKARAN SUJATHA ,  SHAW THOMAS M ,  SIMON ANDREW H ,  STAMPER ANTHONY K

IPC: H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC classification number: B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device of high strength that lowers an effective dielectric constant k eff , maintains an inter-level vertical capacity in an interconnection at a low level and a manufacturing method of the same. SOLUTION: The method of manufacturing the device comprises a step for providing a structure having an insulating layer 120 of at least one interconnection 130 and a step for forming a sublithographic template mask 150 on the insulating layer. A sublithographic feature 135a is formed in the vicinity of at least one intereconnection by performing etching on the insulating layer through the sublithographic template mask using a selective etching step. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种降低有效介电常数k eff 的高强度半导体器件，将互连中的级间垂直容量保持在低水平，并且制造方法 一样的。 解决方案：制造该器件的方法包括提供具有至少一个互连130的绝缘层120和在绝缘层上形成亚光刻模板掩模150的步骤的结构的步骤。 通过使用选择性蚀刻步骤，通过通过亚光刻模板掩模对绝缘层进行蚀刻，在至少一个相互连接附近形成亚光刻部件135a。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004214648A

公开(公告)日：2004-07-29

申请号：JP2003421653

申请日：2003-12-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COLBURN MATTHEW E ,  HUANG ELBERT E ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SAENGER KATHERINE L

IPC: H01L23/12 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming in-layer and interlayer air bridge structures, in a large scale integrated circuit (VLSI) device, a very large scale integrated circuit (ULSI) device, and a high-performance package. SOLUTION: The method of forming low k (dielectric constant) and ultra-low k multilayer mutual connections on a substrate is provided with a process to form a pair of mutual connection, separated along a side face by an air gap and a support layer in a via level of a dual damascene structure which exists only under a metal wiring, a process to remove a sacrificial dielectric through a holed bridge layer to connect an upper surface of the mutual connection along the side face, a process of executing a multilayer level extraction of the sacrificial layer, a process of sealing the bridge by a controlled method, and a process of reducing the effective dielectric constant of a film holed by using a patterning technology of a quasi-optical lithography. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：WO2004068550A3

公开(公告)日：2005-10-27

申请号：PCT/US2004002125

申请日：2004-01-26

Applicant: IBM ,  COHEN STEPHEN A ,  GATES STEPHAN M ,  HEDRICK JEFFREY C ,  HUANG ELBERT E ,  PFEIFFER DIRK

Inventor： COHEN STEPHEN A ,  GATES STEPHAN M ,  HEDRICK JEFFREY C ,  HUANG ELBERT E ,  PFEIFFER DIRK

IPC: H01L20060101 ,  H01L21/00 ,  H01L21/312 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L21/02282 ,  H01L21/02126 ,  H01L21/02222 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3125 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31663 ,  H01L2924/00

Abstract: The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween where the ceramic diffusion barrier has a composition, SivNwCxOyHz, where 0.1

Abstract translation: 本发明包括在其间形成的金属，层间电介质和陶瓷扩散阻挡层的互连结构，其中陶瓷扩散阻挡层具有组成SivNwCxOyHz，其中0.1 <= v <= 0.9,0 <= w <= 0.5,0.01 < = x <= 0.9,0 <= y <= 0.7,0.01 <= z <= 0.8对于v + w + x + y + Z = 1。 陶瓷扩散阻挡层用作金属的扩散阻挡层，即铜。 本发明还包括一种用于形成本发明的陶瓷扩散阻挡层的方法，包括沉积具有组成SivNwCxOyHz的聚合物预陶瓷的步骤，其中0.1

公开(公告)号：WO2004095510A3

公开(公告)日：2006-02-02

申请号：PCT/US2004010443

申请日：2004-04-05

Applicant: IBM ,  HEDRICK JEFFREY C ,  HUANG ELBERT E

Inventor： HEDRICK JEFFREY C ,  HUANG ELBERT E

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/312 ,  H01L21/314 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76832 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3121 ,  H01L21/314 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures having low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer are described herein. The multilayered dielectric diffusion barrier layer are diffusion barriers to metal and barriers to air permeation. Methods and compositions relating to the generation of the structures are also described. The advantages of utilizing these low-k multilayered dielectric diffusion barrier layer is a gain in chip performance through a reduction in capacitance between conducting metal features and an increase in reliability as the multilayered dielectric diffusion barrier layer are impermeable to air and prevent metal diffusion.

Abstract translation: 本文描述了具有至少一个低k​​子层和至少一个空气阻挡子层的具有低k多层介电扩散阻挡层的结构。 多层电介质扩散阻挡层是对金属的扩散屏障和空气渗透屏障。 还描述了与生成结构有关的方法和组合物。 利用这些低k多层电介质扩散阻挡层的优点是通过降低导电金属特性之间的电容并且随着多层电介质扩散阻挡层对空气不透气并防止金属扩散而增加可靠性，可以提高芯片性能。

公开(公告)号：WO2005122195A3

公开(公告)日：2006-06-22

申请号：PCT/US2005018196

申请日：2005-05-23

Applicant: IBM ,  HUANG ELBERT E ,  KIM HYUNGJUN ,  MILLER ROBERT D ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH

Inventor： HUANG ELBERT E ,  KIM HYUNGJUN ,  MILLER ROBERT D ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH

IPC: H01L21/302 ,  H01G13/00 ,  H01L21/311 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/3121 ,  H01L21/3125 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interconnect structures are fabricated by methods that comprise depositing a thin conformal passivation dielectric and/or diffusion barrier cap and/or hard mask by an atomic layer deposition or supercritical fluid based process.

Abstract translation: 通过包括通过原子层沉积或基于超临界流体的方法沉积薄的共形钝化介质和/或扩散阻挡盖和/或硬掩模的方法来制造互连结构。

公开(公告)号：WO2004068551A3

公开(公告)日：2005-05-26

申请号：PCT/US2004002126

申请日：2004-01-26

Applicant: IBM ,  GATES STEPHEN M ,  HEDRICK JEFFREY C ,  HUANG ELBERT E ,  PFEIFFER DIRK

Inventor： GATES STEPHEN M ,  HEDRICK JEFFREY C ,  HUANG ELBERT E ,  PFEIFFER DIRK

IPC: G03G13/06 ,  H01L20060101 ,  H01L21/00 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/44 ,  H01L23/48 ,  H05B6/64

CPC classification number: H01L21/02126 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3125 ,  H01L21/316 ,  Y10S430/146 ,  Y10T428/31663

Abstract: The present invention comprises a method for forming a hardmask including the steps of depositing a polymeric preceramic precursor film atop a substrate; converting the polymeric preceramic precursor film into at least one ceramic layer, where the ceramic layer has a composition of SivNWCXOyHZ where 0.1

Abstract translation: 本发明包括一种用于形成硬掩模的方法，包括以下步骤：在基底顶上沉积聚合物预陶瓷前体膜; 将聚合物陶瓷前体膜转化为至少一个陶瓷层，其中陶瓷层具有SivNWCXOyHZ的组成，其中0.1≤v≤0.9,0<= w <0.5,0.05 <= x <= 0.9,0