ALIGNMENT SYSTEM FOR SUBASSEMBLY OF OVERMOLDED PHOTOELECTRIC MODULE

    公开(公告)号:JP2002043342A

    公开(公告)日:2002-02-08

    申请号:JP2001137796

    申请日:2001-05-08

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a method by which positioning of a laminate substrate or other substrates on a mold base is improved. SOLUTION: This alignment system of a photoelectric module has an overmolded chip carrier 26 and positions a substrate in a mold precisely to form an overmold frame 18 on the substrate. Co-operating stand-off pads 70, 71, 72 in a retainer assembly on the overmold frame stabilize an assembly of these components, and provide precise gaps to bond these two components permanently. The retainer assembly 36 has a co-operating feature for positioning an end electric lead of a flexible circuit in an electric pad array on the substrate. A nearby electric lead is protected by a permanent enclosing plate on a nearby edge portion of the flexible circuit and positioned by optic dies and an electric pad on their carriers.

    ENHANCED COUPLING ARRANGEMENT FOR AN OPTOELECTRONIC TRANSDUCER

    公开(公告)号:MY134293A

    公开(公告)日:2007-12-31

    申请号:MYPI20014059

    申请日:2001-08-29

    Applicant: IBM

    Abstract: A COUPLING ARRANGEMENT INCLUDES A VERTICAL CAVITY SURFACE EMITTING LASER. A CARRIER (22) HAS THE VERTICAL CAVITY SURFACE EMITTING LASER AFFIXED THERETO. AN OPTICAL COUPLER (26) IS COUPLED TO THE VERTICAL CAVITY SURFACE EMITTING LASER, AND HAS A PLURALITY OF OPTICAL FIBERS (38) WHICH RECEIVE LIGHT EMITTED FROM THE VERTICAL CAVITY SURFACE EMITTING LASER. THE VERTICAL CAVITY SURFACE EMITTING LASER IS SEPARATED FROM THE OPTICAL COUPLER BY A GAP (30) AND IS FREE OF DIRECT CONTACT WITH THE OPTICAL COUPLER. THE GAP IS LESS THAN ABOUT 50 MICRONS, AND IS GREATER THAN ZERO MICRONS. A CURABLE ADHESIVE (28) IS DISPOSED IN THE GAP FOR COUPLING THE VERTICAL CAVITY SURFACE EMITTING LASER TO THE OPTICAL COUPLER. THE ADHESIVE HAS A VISCOSITY THAT DEFINES A SIZE OF THE GAP.(FIG. 3)

    7.
    发明专利
    未知

    公开(公告)号:DE69308390D1

    公开(公告)日:1997-04-10

    申请号:DE69308390

    申请日:1993-06-07

    Applicant: IBM

    Abstract: This invention relates to three dimensional packaging of integrated circuit chips into stacks to form cube structures. Between adjacent chips in the stack, there is disposed an electrical interconnection means which is a first substrate having a plurality of conductors one end of which is electrically connected to chip contact locations and the other end of which extends to one side of the chip stack to form a plurality of pin-like electrical interconnection assemblies. The pin-like structures can be formed from projections of the first substrate having an electrical conductor on at least one side thereof extending from this side. Alternatively, the pin-like structures can be formed from conductors which cantilever from both sides of an edge of the first substrate corresponding conductors from both sides are aligned and spaced apart by the first substrate thickness. The spaces contains solder and form solder loaded pin-like structures. The pin-like structures can be directly solder bonded to conductors on a second substrate surface or the pin-like structures can be adapted for insertion into apertures in a second substrate. The second substrate provides a means for electrically interconnecting a plurality of these cubes. Preferably, the first and second substrates are circuitized flexible polymeric films. The second substrate is disposed on a third substrate, such as a PC board, with a resilient material therebetween which permits a heat sink to be pressed into intimate contact with an opposite side of the cube.

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