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公开(公告)号：US6436803B2
公开(公告)日：2002-08-20
申请号：US84043201
申请日：2001-04-23
Applicant: IBM
Inventor： BHATT ANILKUMAR CHINUPRASAD , MAGNUSON ROY HARVEY , MILLER THOMAS RICHARD , MARKOVICH VOYA RISTA , SAMBUCETTI CARLOS J , TISDALE STEPHEN LEO
IPC: H05K3/38 , C23C18/16 , H01L23/12 , H01L25/065 , H01L25/07 , H01L25/18 , H05K3/18 , H05K3/46 , H01L21/44
CPC classification number: H05K3/181 , C23C18/1632 , C23C18/2086 , H01L2224/16 , H01L2924/01046 , H01L2924/01078 , H01L2924/01322 , H01L2924/15312 , Y10T29/49126 , Y10T29/49165
Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface and laminating a metal foil onto the substrate. The metal foil is patterned to form a first wiring layer. A permanent photoimagable dielectric layer is formed over the wiring layer and via holes are formed through the dielectric layer over pads and conductors of the wiring layer. Holes are formed through the substrate and substrate surfaces including the photoimagable dielectric, walls of the via holes, and walls of the through holes subjected to an electroless copper plating process. The process includes seeding the surface, coating the surface with a first solution containing surfactant and electroplating in a second solution in which the level of surfactant is regulated by determining the surface tension and metering surfactant addition to the second solution depending on the determination of surface tension. The copper plating on the photoimagable dielectric is patterned to form an exterior wiring layer which is covered by solder resist with windows over lands around the through holes and surface mount connection pads of the exterior wiring layer to form a high density circuitized substrate. Surface mount components and/or pin in hole components are attached to the circuitized substrate with solder joints between terminals of the components and the lands and/or connection pads to form a high density circuit board assembly. One or more of the circuit board assemblies are mounted in an enclosure with a power supply, CPU, RAM, and I/O means to form an information handling system with increased performance due to shorter signal flight times due to the higher device density.
Abstract translation: 通过形成具有电介质表面的基板并将金属箔层压到基板上来制造电路板。 图案化金属箔以形成第一布线层。 在布线层上方形成永久的光致可变电介质层，并且通过布线层的焊盘和导体上的电介质层形成通孔。 通过基板和基板表面形成孔，包括可光成像的电介质，通孔的壁和穿过无电镀铜工艺的通孔的壁。 该方法包括接种表面，用含有表面活性剂的第一溶液涂覆表面和在第二溶液中电镀，其中通过根据表面张力的测定确定表面张力和计量表面活性剂添加到第二溶液中来调节表面活性剂的含量 。 对可光成像电介质上的镀铜进行图案化以形成外部布线层，该外部布线层由通过孔周围的窗口和外部布线层的表面安装连接焊盘覆盖的阻焊剂覆盖，以形成高密度电路化基板。 表面安装部件和/或销孔部件通过部件的端子与焊盘和/或连接焊盘之间的焊接点附接到电路化的基板，以形成高密度电路板组件。 一个或多个电路板组件安装在具有电源，CPU，RAM和I / O装置的外壳中，由于更高的器件密度，由于更短的信号飞行时间，从而形成具有增加的性能的信息处理系统。
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Patent Agency Ranking
公开(公告)号：BR8900664A
公开(公告)日：1989-10-10
申请号：BR8900664
申请日：1989-02-15
Applicant: IBM
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公开(公告)号：DE3685241D1
公开(公告)日：1992-06-17
申请号：DE3685241
申请日：1986-02-28
Applicant: IBM
Inventor： KASCHAK RONALD ANTHONY , MAGNUSON ROY HARVEY , YARMCHUK EDWARD JOHN
Abstract: Method for controlling plating in an electroless plating process. The plating rate is continuously monitored. The plating rate is compared with a set point plating rate. A control voltage is derived proportional to the difference in .plating rate and the desired plating rate, the integral of the difference, and the derivative of the difference. The control voltage is applied to a replenishment control for controlling the replenishment rate of a constituent chemical of the plating process.
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公开(公告)号：DE3584233D1
公开(公告)日：1991-10-31
申请号：DE3584233
申请日：1985-10-17
Applicant: IBM
Inventor： MAGNUSON ROY HARVEY , SCHUBERT STEVEN ASHLEY
Abstract: The quantity of an anionic material in a sample is determined by adjusting the pH of the sample to place the material in nonionic extractable form, extracting out the material, spectrophotometrically measuring the extracted material, and comparing the measured value to a standard in order to determine the quantity of the anionic material.
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