公开(公告)号：EP1841558A4

公开(公告)日：2012-04-04

申请号：EP05852628

申请日：2005-12-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER ENAMUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMANIAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

IPC: B23H3/00 ,  B23H5/08

CPC classification number: C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

公开(公告)号：JP2004162177A

公开(公告)日：2004-06-10

申请号：JP2003348876

申请日：2003-10-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ECONOMIKOS LAERTIS ,  DELIGIANNI HARIKLIA ,  COTTE JOHN M ,  ANDRICACOS PANAYOTIS C

IPC: C25D5/04 ,  C25D5/48 ,  C25D7/12 ,  C25D17/00 ,  C25D21/00 ,  C25F3/12 ,  C25F7/00 ,  H01L21/288

CPC classification number: C25D5/48 ,  C25D17/00 ,  C25D17/001 ,  C25D17/10

Abstract: PROBLEM TO BE SOLVED: To provide an integrated plating and planarization apparatus having a counter electrode with a variable diameter.
SOLUTION: The apparatus for plating and planarizing a metal on a substrate is provided with a plurality of distribution segments each of which has at least one hole for distributing an electroplating solution onto the substrate. The distribution segments form a circular counter electrode and is movable with respect to each other during an electroplating process so that the counter electrode may have a variable diameter. Thus, the electroplating solution is distributed onto the annular part of the substrate having a diameter corresponding to the diameter of the counter electrode. Therefore, the counter electrode can allow the local delivery of the plating solution onto the substrate.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2005217419A

公开(公告)日：2005-08-11

申请号：JP2005021309

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  ANDRICACOS PANAYOTIS C ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  MAGERLEIN JOHN H ,  PETRARCA KEVIN S ,  STEIN KENNETH JAY ,  VOLANT RICHARD P

IPC: H01F41/04 ,  H01F17/00 ,  H01L21/02 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/08

CPC classification number: H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an inductor and a method of forming the inductor. SOLUTION: The method of forming the inductor comprises (a) a step for providing a semiconductor substrate, (b) a step for forming a dielectric layer on the surface of the substrate, (c) a step for forming a lower trench in the dielectric layer, (d) a step for forming a resist layer on the surface of the dielectric layer, (e) a step for forming an upper trench which is aligned to the lower trench and whose bottom is opened for the lower trench in the resist layer, and (f) a step for completely filling the lower trench with a conductor and at least partially filling the upper trench with the conductor to form the inductor. The semiconductor structure includes the inductor including the upper surface, bottom surface and sidewall and a means that allows the inductor to be electrically contacted, the lower section of the inductor is extended by a distance that the lower section of the inductor is fixed in the dielectric layer formed on the substrate, and the upper section thereof is extended on the dielectric layer. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供电感器和形成电感器的方法。 形成电感器的方法包括（a）提供半导体衬底的步骤，（b）在衬底的表面上形成电介质层的步骤，（c）形成下沟槽的步骤 在电介质层中，（d）在电介质层的表面上形成抗蚀剂层的步骤，（e）形成上沟槽的步骤，该上沟槽与下沟槽对准并且底部为下沟槽开口 抗蚀剂层，和（f）用导体完全填充下沟槽并且至少部分地用导体填充上沟槽以形成电感器的步骤。 半导体结构包括电感器，其包括上表面，底表面和侧壁，以及允许电感器电接触的装置，电感器的下部延伸一段距离，电感器的下部固定在电介质中 层，其上部在电介质层上延伸。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2006088533A3

公开(公告)日：2007-09-27

申请号：PCT/US2005043464

申请日：2005-12-02

Applicant: IBM ,  ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER EMANUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

Inventor： ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER EMANUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

IPC: B23H3/00

CPC classification number: C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

Abstract: Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

Abstract translation: 提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。 所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

公开(公告)号：DE69637333T2

公开(公告)日：2008-10-02

申请号：DE69637333

申请日：1996-06-12

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS C ,  DELIGIANNI HARIKLIA ,  HARPER JAMES MCKELL EDWIN ,  HU CHAO-KUN ,  PEARSON DALE JONATHAN ,  REYNOLDS SCOTT KEVIN ,  TU KING-NING ,  UZOH CYPRIAN EMEKA

IPC: C22C9/00 ,  H01L23/532 ,  C22C9/02 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498

Abstract: Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and a method of making such interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.

公开(公告)号：DE69637333D1

公开(公告)日：2008-01-10

申请号：DE69637333

申请日：1996-06-12

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS C ,  DELIGIANNI HARIKLIA ,  HARPER JAMES MCKELL EDWIN ,  HU CHAO-KUN ,  PEARSON DALE JONATHAN ,  REYNOLDS SCOTT KEVIN ,  TU KING-NING ,  UZOH CYPRIAN EMEKA

IPC: C22C9/00 ,  H01L23/532 ,  C22C9/02 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498

Abstract: Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and a method of making such interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.