公开(公告)号：WO0199160A3

公开(公告)日：2002-10-17

申请号：PCT/US0119684

申请日：2001-06-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： SCHNABEL RAINER FLORIAN ,  RADENS CARL J ,  LANDIS HOWARD ,  PARK YOUNG JIN ,  KOTECKI DAVID ,  REITH ARMIN M ,  TRICKLE WAYNE ,  WORDEMAN MATTHEW R

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10808

Abstract: A semiconductor memory device (100), in accordance with the present invention, includes a substrate having a major surface including an array region (102) and a support region (104). The array region includes memory cell structures (106) having a first height above the major surface of the substrate. The support area includes dummy structures (119) formed therein having a second height above the major surface. A dielectric layer (118) is formed over the memory cell structures in the array region and the dummy structures in the support region such that a top surface (122) of the dielectric layer is substantially planar wherein topographical features are substantially eliminated on the dielectric layer across the array region and the support region.

Abstract translation: 根据本发明的半导体存储器件（100）包括具有包括阵列区域（102）和支撑区域（104）的主表面的衬底。 阵列区域包括在衬底的主表面上方具有第一高度的存储单元结构（106）。 支撑区域包括形成在其中的在主表面上方具有第二高度的虚拟结构（119）。 在阵列区域中的存储单元结构和支撑区域中的虚拟结构之间形成电介质层（118），使得电介质层的顶表面（122）基本上是平面的，其中在介电层上基本上消除了形貌特征 跨越阵列区域和支撑区域。

公开(公告)号：JP2002016070A

公开(公告)日：2002-01-18

申请号：JP2001171050

申请日：2001-06-06

Applicant: IBM

Inventor： LAWRENCE ALFRED CLEVENGER ,  RONALD JEAN PHILIPPI ,  RODBELL KENNETH PARKER ,  ROY CHARLES IGGULDEN ,  CHAOKUN FUU ,  LINN MARIE GIGNAC ,  WEBER STEPHAN ,  GAMBINO JEFFREY PETER ,  SCHNABEL RAINER FLORIAN

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a dual damascene process that can reliably form aluminum interconnection exhibiting improved electro migration characteristics, as compared with aluminum interconnection that is formed by the conventional RIE technique. SOLUTION: More specifically, the dual damascene process depends on a PVD-Ti/CVD-TiN barrier layer and forms an aluminum line showing great reduction in a saturation resistance level, the inhibition of the electro migration, or both of them especially in a line longer than 100 micrometers. The electromigration life time of the dual damascene aluminum line depends greatly on the conditions of materials and material-filling processes. When there is deviation in the materials and treatment, the electromigration life time way possibly become shorter than life time that is achieved by an aluminum RIE interconnection line, and this becomes a serious matter.

公开(公告)号：JP2000195860A

公开(公告)日：2000-07-14

申请号：JP37512499

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： SCHNABEL RAINER FLORIAN ,  RONALD PHILLIPI ,  HOINKIS MARK ,  WEBER STEFAN ,  ROY IGARUDEN ,  WEIGAND PETER ,  LAWRENCE CLEVENGER

IPC: H01L23/52 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To increase the electromigration lifetime of a semiconductor device by stacking a liner by an ionizing metal plasma physical deposition method, thereby reducing the mass carriage by electromigration. SOLUTION: A dielectric layer is made on a substrate. The dielectric layer is patterned, and a contact hole 26 is made, and conductive material is stacked on a dielectric layer so as to fill the contact hole 26 and cover the dielectric layer. Next, excess material is removed by polishing from the surface 29 so as to make a flat surface for an additional layer. Next, a liner 40 is stacked on the dielectric layer 29. This liner consists of a material having high electromigration resistance. For example, titanium(Ti) and its alloy tantalum(Ta) and its alloy, or TiN or Tan is included as such a liner material. This liner 40 is stacked, using an ionizing metal plasma physical deposition method.