Abstract:
A semiconductor memory device (100), in accordance with the present invention, includes a substrate having a major surface including an array region (102) and a support region (104). The array region includes memory cell structures (106) having a first height above the major surface of the substrate. The support area includes dummy structures (119) formed therein having a second height above the major surface. A dielectric layer (118) is formed over the memory cell structures in the array region and the dummy structures in the support region such that a top surface (122) of the dielectric layer is substantially planar wherein topographical features are substantially eliminated on the dielectric layer across the array region and the support region.
Abstract:
PROBLEM TO BE SOLVED: To provide a dual damascene process that can reliably form aluminum interconnection exhibiting improved electro migration characteristics, as compared with aluminum interconnection that is formed by the conventional RIE technique. SOLUTION: More specifically, the dual damascene process depends on a PVD-Ti/CVD-TiN barrier layer and forms an aluminum line showing great reduction in a saturation resistance level, the inhibition of the electro migration, or both of them especially in a line longer than 100 micrometers. The electromigration life time of the dual damascene aluminum line depends greatly on the conditions of materials and material-filling processes. When there is deviation in the materials and treatment, the electromigration life time way possibly become shorter than life time that is achieved by an aluminum RIE interconnection line, and this becomes a serious matter.
Abstract:
PROBLEM TO BE SOLVED: To increase the electromigration lifetime of a semiconductor device by stacking a liner by an ionizing metal plasma physical deposition method, thereby reducing the mass carriage by electromigration. SOLUTION: A dielectric layer is made on a substrate. The dielectric layer is patterned, and a contact hole 26 is made, and conductive material is stacked on a dielectric layer so as to fill the contact hole 26 and cover the dielectric layer. Next, excess material is removed by polishing from the surface 29 so as to make a flat surface for an additional layer. Next, a liner 40 is stacked on the dielectric layer 29. This liner consists of a material having high electromigration resistance. For example, titanium(Ti) and its alloy tantalum(Ta) and its alloy, or TiN or Tan is included as such a liner material. This liner 40 is stacked, using an ionizing metal plasma physical deposition method.