公开(公告)号：EP1875508A4

公开(公告)日：2009-08-05

申请号：EP06750977

申请日：2006-04-21

Applicant: IBM

Inventor： DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

IPC: H01L29/04

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

Abstract: Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.

公开(公告)号：JP2010267964A

公开(公告)日：2010-11-25

申请号：JP2010109553

申请日：2010-05-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YUAN JUN ,  YIN HAIZHOU ,  LIANG YUE ,  YU XIAOJUN ,  FANG SUNFEI ,  CHIDAMBARRAO DURESETI

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L21/28132 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/6659 ,  H01L29/7835 ,  Y10S257/90

Abstract: PROBLEM TO BE SOLVED: To provide an asymmetric semiconductor device, and to provide a method using a spacer scheme in manufacturing the same. SOLUTION: A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high-k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the second portion. The first portion of the asymmetric gate stack includes, from bottom to top, a threshold voltage adjusting material and at least a first conductive spacer, while the second portion of the asymmetric gate stack includes at least a second conductive spacer over the gate dielectric. In some embodiments, the second conductive spacer is in direct contact with the underlying high-k gate dielectric, while, in other embodiments, the first and second conductive spacers are in direct contact with the threshold voltage adjusting material. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种非对称半导体器件，并提供一种使用间隔方案制造该方法的方法。 解决方案：提供了一种半导体结构，其包括位于高k栅极电介质的表面上的不对称栅极堆叠。 非对称栅极堆叠包括第一部分和第二部分，其中第一部分具有与第二部分不同的阈值电压。 不对称栅极堆叠的第一部分包括从底部到顶部的阈值电压调节材料和至少第一导电间隔物，而非对称栅极堆叠的第二部分包括在栅极电介质上的至少第二导电间隔物。 在一些实施例中，第二导电间隔物与下面的高k栅极电介质直接接触，而在其它实施例中，第一和第二导电间隔物与阈值电压调节材料直接接触。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011018904A

公开(公告)日：2011-01-27

申请号：JP2010151970

申请日：2010-07-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LUO ZHIJIONG ,  ZHU HUILONG ,  LIANG QINGQING ,  YIN HAIZHOU

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/41 ,  H01L29/417

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/1203 ,  H01L29/7843 ,  H01L29/7848

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal-oxide film semiconductor (CMOS) device that is free from causing troubles in contact formation by a stress liner, and to provide a method of manufacturing the device.SOLUTION: The complementary metal-oxide film semiconductor (CMOS) device is prepared with a constitution having a silicon-dioxide layer 102 on a silicon-substrate layer, and a concave source/drain trench. A nitride stress liner 104 is deposited in the concave source/drain trench, and further an oxide layer 106 is deposited thereon. The CMOS device is set on a handling wafer, the silicon-substrate layer is removed, and the silicon-dioxide layer 102 is etched to form an opening in contact with part of a source/drain region 170. Resultantly, a contact 180 is formed.

Abstract translation: 要解决的问题：提供一种互补的金属氧化物半导体（CMOS）器件，其不会引起应力衬垫的接触形成的麻烦，并且提供一种制造器件的方法。解决方案：互补金属氧化物膜 半导体（CMOS）器件通过在硅衬底层上具有二氧化硅层102和凹入的源/漏沟槽的结构来制备。 氮化物应力衬垫104沉积在凹形源/漏沟槽中，并且另外在其上沉积氧化物层106。 将CMOS器件设置在处理晶片上，去除硅衬底层，并且蚀刻二氧化硅层102以形成与源极/漏极区域170的一部分接触的开口。结果，形成接触件180 。

公开(公告)号：EP1886342A4

公开(公告)日：2011-06-15

申请号：EP06770646

申请日：2006-05-18

Applicant: IBM

Inventor： FOGEL KEITH E ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YIN HAIZHOU

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/8236

CPC classification number: H01L21/2022 ,  H01L21/76224 ,  H01L21/823807

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.

公开(公告)号：WO2006130360A3

公开(公告)日：2007-06-14

申请号：PCT/US2006019417

申请日：2006-05-18

Applicant: IBM ,  FOGEL KEITH E ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YIN HAIZHOU

Inventor： FOGEL KEITH E ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YIN HAIZHOU

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/8236

CPC classification number: H01L21/2022 ,  H01L21/76224 ,  H01L21/823807

Abstract: The present invention provides an improved amorphization/ templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of "corner defects" at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprisng the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches; (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.

Abstract translation: 本发明提供了用于制造低缺陷密度混合取向基底的改进的非晶化/模板重结晶（ATR）方法。 用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。 第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板，再结晶成第二Si层的取向。 本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽限定的非晶化Si区域的边缘处产生“角部缺陷”，以及在高温后再结晶缺陷 - 不由沟槽限定的非ATR区域的去除退火。 特别地，本发明提供一种工艺流程，包括以下步骤：（i）在没有沟槽的衬底区域中进行的非晶化和低温重结晶; （ii）形成沟槽隔离区域，其包围在ATR'd区域的边缘处的缺陷区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

公开(公告)号：WO2011056336A3

公开(公告)日：2011-07-28

申请号：PCT/US2010051383

申请日：2010-10-05

Applicant: IBM ,  YIN HAIZHOU ,  WANG XINHUI ,  CHAN KEVIN K ,  REN ZHIBIN

Inventor： YIN HAIZHOU ,  WANG XINHUI ,  CHAN KEVIN K ,  REN ZHIBIN

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/26586 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7835

Abstract: The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.

Abstract translation: 本发明提供了形成非对称场效应晶体管的方法。 所述方法包括在半导体衬底的顶部上形成栅极结构，所述栅极结构包括栅极叠层和邻近所述栅极堆叠的侧壁的间隔物，并且具有与所述第一侧相对的第一侧和第二侧; 从衬底中的栅极结构的第一侧进行成角度的离子注入，从而形成与第一侧相邻的离子注入区域，其中栅极结构防止成角度的离子注入到达邻近第二侧的衬底 门结构; 以及在栅极结构的第一和第二侧在衬底上进行外延生长。 结果，在离子注入区域上的外延生长比经历无离子注入的区域慢得多。 通过外延生长形成到栅极结构的第二侧的源极区域的高度高于通过外延生长形成于栅极结构的第一侧的漏极区域的高度。 还提供了由此形成的半导体结构。

公开(公告)号：WO2006116098A3

公开(公告)日：2008-10-30

申请号：PCT/US2006015107

申请日：2006-04-21

Applicant: IBM ,  DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

Inventor： DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

IPC: H01L29/04

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

Abstract: In the claimed mixed-crystal-orientation channel FET, source/drain regions above the bonded interface 360 have the orientation of the upper semiconductor 350 and source/drain regions below the bonded interface 360 have the orientation of the lower semiconductor 370, so that each part of the source/drain has the same crystal orientation as the semiconductor material laterally adjacent to it. Optional source/drain extensions 392 are disposed entirely in the upper semiconductor layer 350. Optionally, the bonded interface 360 is situated towards the bottom of source/drain regions 380, leaving source/drains 380 mostly in upper semiconductor layer 350.

Abstract translation: 在所要求的混晶取向沟道FET中，键合界面360上方的源极/漏极区域具有上部半导体350的取向，并且键合界面360下方的源极/漏极区域具有下部半导体370的取向，使得每个 源极/漏极的一部分具有与横向相邻的半导体材料相同的晶体取向。 可选的源极/漏极延伸部分392完全设置在上部半导体层350中。可选地，接合界面360朝向源极/漏极区域380的底部设置，使得源极/漏极380大部分在上部半导体层350中。

公开(公告)号：GB2487870B

公开(公告)日：2013-12-25

申请号：GB201207819

申请日：2010-10-05

Applicant: IBM

Inventor： YIN HAIZHOU ,  WANG XINHUI ,  CHAN KEVIN K ,  REN ZHIBIN

IPC: H01L21/265 ,  H01L29/66 ,  H01L29/78

Abstract: The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.

公开(公告)号：DE112010004330B4

公开(公告)日：2014-03-06

申请号：DE112010004330

申请日：2010-10-05

Applicant: IBM

Inventor： YIN HAIZHOU ,  WANG XINHUI ,  CHAN KEVIN K ,  REN ZHIBIN

IPC: H01L21/336 ,  H01L29/78

Abstract: Die vorliegende Erfindung stellt ein Verfahren zum Bilden asymmetrischer Feldeffekttransistoren bereit. Das Verfahren umfasst das Bilden einer Gate-Struktur auf einem Halbleitersubstrat, wobei die Gate-Struktur einen Gate-Stapel und Abstandhalter in Nachbarschaft zu Seitenwänden des Gate-Stapels umfasst und eine erste Seite und eine zweite Seite gegenüber der ersten Seite aufweist; das Durchführen einer schrägen Ionenimplantation von der ersten Seite der Gate-Struktur in dem Substrat, wodurch eine Zone mit Ionenimplantation in Nachbarschaft zu der ersten Seite gebildet wird, wobei die Gate-Struktur verhindert, dass die schräge Ionenimplantation das Substrat in Nachbarschaft zu der zweiten Seite der Gate-Struktur erreicht; und das Durchführen eines epitaxialen Anwachsens auf dem Substrat auf der ersten und zweiten Seite der Gate-Struktur. Als Ergebnis ist das epitaxiale Anwachsen auf dem Bereich mit Ionenimplantation viel langsamer als auf einem Bereich, welcher keine Ionenimplantation erfährt. Eine Source-Zone, welche durch das epitaxiale Anwachsen auf der zweiten Seite der Gate-Struktur gebildet wird, weist eine Höhe auf, die größer ist als die einer Drain-Zone, welche durch das epitaxiale Anwachsen auf der ersten Seite der Gate-Struktur gebildet wird. Eine dadurch gebildete Halbleiterstruktur wird ebenfalls bereitgestellt.

公开(公告)号：DE112010004330T5

公开(公告)日：2012-09-06

申请号：DE112010004330

申请日：2010-10-05

Applicant: IBM

Inventor： YIN HAIZHOU ,  WANG XINHUI ,  CHAN KEVIN K ,  REN ZHIBIN

IPC: H01L21/336 ,  H01L29/78

Abstract: Die vorliegende Erfindung stellt ein Verfahren zum Bilden asymmetrischer Feldeffekttransistoren bereit. Das Verfahren umfasst das Bilden einer Gate-Struktur auf einem Halbleitersubstrat, wobei die Gate-Struktur einen Gate-Stapel und Abstandhalter in Nachbarschaft zu Seitenwänden des Gate-Stapels umfasst und eine erste Seite und eine zweite Seite gegenüber der ersten Seite aufweist; das Durchführen einer schrägen Ionenimplantation von der ersten Seite der Gate-Struktur in dem Substrat, wodurch eine Zone mit Ionenimplantation in Nachbarschaft zu der ersten Seite gebildet wird, wobei die Gate-Struktur verhindert, dass die schräge Ionenimplantation das Substrat in Nachbarschaft zu der zweiten Seite der Gate-Struktur erreicht; und das Durchführen eines epitaxialen Anwachsens auf dem Substrat auf der ersten und zweiten Seite der Gate-Struktur. Als Ergebnis ist das epitaxiale Anwachsen auf dem Bereich mit Ionenimplantation viel langsamer als auf einem Bereich, welcher keine Ionenimplantation erfährt. Eine Source-Zone, welche durch das epitaxiale Anwachsen auf der zweiten Seite der Gate-Struktur gebildet wird, weist eine Höhe auf, die größer ist als die einer Drain-Zone, welche durch das epitaxiale Anwachsen auf der ersten Seite der Gate-Struktur gebildet wird. Eine dadurch gebildete Halbleiterstruktur wird ebenfalls bereitgestellt.