公开(公告)号：EP1886342A4

公开(公告)日：2011-06-15

申请号：EP06770646

申请日：2006-05-18

Applicant: IBM

Inventor： FOGEL KEITH E ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YIN HAIZHOU

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/8236

CPC classification number: H01L21/2022 ,  H01L21/76224 ,  H01L21/823807

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.

公开(公告)号：EP1875508A4

公开(公告)日：2009-08-05

申请号：EP06750977

申请日：2006-04-21

Applicant: IBM

Inventor： DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

IPC: H01L29/04

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

Abstract: Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.

公开(公告)号：WO2006130360A3

公开(公告)日：2007-06-14

申请号：PCT/US2006019417

申请日：2006-05-18

Applicant: IBM ,  FOGEL KEITH E ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YIN HAIZHOU

Inventor： FOGEL KEITH E ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YIN HAIZHOU

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/8236

CPC classification number: H01L21/2022 ,  H01L21/76224 ,  H01L21/823807

Abstract: The present invention provides an improved amorphization/ templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of "corner defects" at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprisng the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches; (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.

Abstract translation: 本发明提供了用于制造低缺陷密度混合取向基底的改进的非晶化/模板重结晶（ATR）方法。 用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。 第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板，再结晶成第二Si层的取向。 本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽限定的非晶化Si区域的边缘处产生“角部缺陷”，以及在高温后再结晶缺陷 - 不由沟槽限定的非ATR区域的去除退火。 特别地，本发明提供一种工艺流程，包括以下步骤：（i）在没有沟槽的衬底区域中进行的非晶化和低温重结晶; （ii）形成沟槽隔离区域，其包围在ATR'd区域的边缘处的缺陷区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

公开(公告)号：WO2006057645A8

公开(公告)日：2006-08-03

申请号：PCT/US2004042179

申请日：2004-12-15

Applicant: IBM ,  CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a -containing layer having a 110 crystal orientation and a biaxial compressive strain. The term ''biaxial compressive stress'' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing 110 layer; and creating a biaxial strain in the silicon-containing 110 layer.

Abstract translation: 本发明提供具有增强的电子和空穴迁移率的半导体材料，其包含具有110晶向和双向压缩应变的含有层。 术语“双轴压缩应力”在本文中用于描述由在制造半导体材料期间在含Si层上感应的纵向压缩应力和横向应力引起的净应力。 本发明的另一方面涉及一种形成本发明的半导体材料的方法。 本发明的方法包括提供含硅110层的步骤; 并在含硅110层中产生双轴应变。

公开(公告)号：DE602004024448D1

公开(公告)日：2010-01-14

申请号：DE602004024448

申请日：2004-12-15

Applicant: IBM

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

公开(公告)号：DE102013210161A1

公开(公告)日：2013-12-19

申请号：DE102013210161

申请日：2013-05-31

Applicant: IBM

Inventor： AVOURIS PHAEDON ,  GARCIA ALBERTO V ,  SUNG CHUN-YUNG ,  XIA FENGNIAN ,  YAN HUGEN

IPC: H01Q17/00

Abstract: Strukturen und Verfahren zum Verdecken eines Objekts vor elektromagnetischer Strahlung bei den Mikrowellen- und Terahertz-Frequenzen beinhalten das Aufbringen einer Vielzahl von dünnen Lagen aus Graphen um das Objekt herum. Zwischenschichten aus einem transparenten dielektrischen Material können zwischen den dünnen Lagen aus Graphen aufgebracht sein, um die Leistungsfähigkeit zu optimieren. In weiteren Ausführungsformen kann das Graphen in eine Anstrichformulierung oder ein Gewebe formuliert und an dem Objekt angebracht sein. Die Strukturen und Verfahren absorbieren wenigstens einen Anteil der elektromagnetischen Strahlung bei den Mikrowellen- und Terabyte-Frequenzen.

公开(公告)号：WO2006116098A3

公开(公告)日：2008-10-30

申请号：PCT/US2006015107

申请日：2006-04-21

Applicant: IBM ,  DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

Inventor： DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

IPC: H01L29/04

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

Abstract: In the claimed mixed-crystal-orientation channel FET, source/drain regions above the bonded interface 360 have the orientation of the upper semiconductor 350 and source/drain regions below the bonded interface 360 have the orientation of the lower semiconductor 370, so that each part of the source/drain has the same crystal orientation as the semiconductor material laterally adjacent to it. Optional source/drain extensions 392 are disposed entirely in the upper semiconductor layer 350. Optionally, the bonded interface 360 is situated towards the bottom of source/drain regions 380, leaving source/drains 380 mostly in upper semiconductor layer 350.

Abstract translation: 在所要求的混晶取向沟道FET中，键合界面360上方的源极/漏极区域具有上部半导体350的取向，并且键合界面360下方的源极/漏极区域具有下部半导体370的取向，使得每个 源极/漏极的一部分具有与横向相邻的半导体材料相同的晶体取向。 可选的源极/漏极延伸部分392完全设置在上部半导体层350中。可选地，接合界面360朝向源极/漏极区域380的底部设置，使得源极/漏极380大部分在上部半导体层350中。

公开(公告)号：WO2006057645A3

公开(公告)日：2006-11-30

申请号：PCT/US2004042179

申请日：2004-12-15

Applicant: IBM ,  CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a -containing layer having a 110 crystal orientation and a biaxial compressive strain. The term ''biaxial compressive stress'' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing 110 layer; and creating a biaxial strain in the silicon-containing 110 layer.

公开(公告)号：WO2006057645A9

公开(公告)日：2006-09-14

申请号：PCT/US2004042179

申请日：2004-12-15

Applicant: IBM ,  CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a -containing layer having a 110 crystal orientation and a biaxial compressive strain. The term ''biaxial compressive stress'' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing 110 layer; and creating a biaxial strain in the silicon-containing 110 layer.

公开(公告)号：DE102013210162A1

公开(公告)日：2013-12-19

申请号：DE102013210162

申请日：2013-05-31

Applicant: IBM

Inventor： AVOURIS PHAEDON ,  GARCIA ALBERTO VALDES ,  SUNG CHUN-YUNG ,  XIA FENGNIAN ,  YAN HUGEN

IPC: H05K9/00 ,  C01B31/04 ,  C09D5/32 ,  C09D5/33

Abstract: Strukturen zum Abschirmen elektromagnetischer Störungen und Verfahren zum Abschirmen eines Objekts vor elektromagnetischer Strahlung bei Frequenzen, die höher als ein Megahertz sind, beinhalten im Allgemeinen das Bereitstellen hoch dotierter dünner Lagen aus Graphen um das abzuschirmende Objekt herum. Die hoch dotierten dünnen Lagen aus Graphen können eine Dotierstoffkonzentration, die höher als > 1e1013 cm–2 ist, die dahingehend wirksam ist, dass die elektromagnetische Strahlung reflektiert wird, oder eine Dotierstoffkonzentration von 1e1013 cm–2 > n > 0 cm–2 aufweisen, die dahingehend wirksam ist, dass die elektromagnetische Strahlung absorbiert wird.