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    ARC FOR IMPROVED CD CONTROL
    1.
    发明专利
    ARC FOR IMPROVED CD CONTROL 失效

    公开(公告)号：JP2000299282A

    公开(公告)日：2000-10-24

    申请号：JP2000086623

    申请日：2000-03-27

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： TOEBBEN DIRK DR ,  LEE GILL YOUNG ,  LU ZHIJIAN

    IPC: G03F7/004 ,  G03F7/09 ,  G03F7/11 ,  G03F7/26 ,  H01L21/027

    Abstract: PROBLEM TO BE SOLVED: To provide an ARC(antireflection coating) layer which effects more improved CD(critical dimension) control, so as to lessen a resist layer in reflectivity in a lithographic process. SOLUTION: This reduction method is carried out in a manner, where an antireflection coating layer 130 is deposited on a board 130, and a resist layer 170 is deposited on the ARC layer 130, where the ARC layer 130 is composed of a first section 135 and a second section 140, the first section 135 operates in an absorption mode, and the reflectivity of the second section 140 is so set as to reduce the reflectivity difference between the first section 135 and the resist layer 170.

    METHOD OF REDUCING POST-DEVELOPMENT DEFECTS IN AND AROUND OPENINGS FORMED IN PHOTORESIST BY USE OF NON-PATTERNED EXPOSURE
    3.
    发明申请
    METHOD OF REDUCING POST-DEVELOPMENT DEFECTS IN AND AROUND OPENINGS FORMED IN PHOTORESIST BY USE OF NON-PATTERNED EXPOSURE 审中-公开
    通过使用非图形化曝光减少光电子体中形成的开放后期发育缺陷的方法

    公开(公告)号：WO0198836A3

    公开(公告)日：2002-04-18

    申请号：PCT/US0119814

    申请日：2001-06-21

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： LU ZHIJIAN ,  THOMAS ALAN ,  GUTMANN ALOIS ,  CHEN KUANG JUNG ,  LAWSON MARGARET

    IPC: G03F7/20 ,  H01L21/027 ,  G03F7/09

    CPC classification number: H01L21/0274 ,  G03F7/2022 ,  G03F7/2037 ,  G03F7/2039 ,  Y10S430/168

    Abstract: In the exposure and development of available deep ultraviolet (DUV) sensitive photoresist it has been observed that following the standard prior art methods of exposure and development results in a high density of undesirable pieces of components of the photoresist material, Blob Defects, remaining on the semiconductor substrate (body). A method of exposing and developing the photoresist material which results in a reduced incidence of these Blob Defects consists of introducing a low level uniform flood exposure of light in addition to the commonly used exposure to patterned light, followed by standard development. The flood exposure is in the range of 5 to 50 % of the dose-to-clear for a non-patterned exposure.

    Abstract translation: 在可用的深紫外（DUV）敏感光刻胶的曝光和显影中，已经观察到遵循现有技术的标准曝光和显影方法导致光致抗蚀剂材料的不希望的部件的高密度，残留在 半导体衬底（主体）。 曝光和显影光致抗蚀剂材料的方法导致这些斑点缺陷的发生率降低，除了通常使用的图案光曝光之外，还引入低等级的均匀泛光曝光，随后进行标准开发。 对于非图案化曝光，洪水暴露在5至50％的剂量清除范围内。

    METHOD OF REDUCING POST-DEVELOPMENT DEFECTS IN AND AROUND OPENINGS FORMED IN PHOTORESIST BY USE OF MULTIPLE DEVELOPMENT/RINSE CYCLES
    4.
    发明申请
    METHOD OF REDUCING POST-DEVELOPMENT DEFECTS IN AND AROUND OPENINGS FORMED IN PHOTORESIST BY USE OF MULTIPLE DEVELOPMENT/RINSE CYCLES 审中-公开
    通过使用多个开发/冲洗周期来减少在光电子装置中形成的开放后期的发展中缺陷的方法

    公开(公告)号：WO0199161A2

    公开(公告)日：2001-12-27

    申请号：PCT/US0119815

    申请日：2001-06-21

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： LU ZHIJIAN ,  THOMAS ALAN ,  GUTMANN ALOIS ,  CHEN KUANG JUNG ,  LAWSON MARGARET

    IPC: G03F7/30 ,  H01L21/00

    CPC classification number: G03F7/3021

    Abstract: In the exposure and development of available deep ultraviolet (DUV) sensitive photoresist it has been observed that following the standard prior art methods of exposure and development results in a high density of undesirable remnants (denoted as Blob Defects) of various components of photoresist material remaining on the semiconductor substrate (body). A method of exposing and developing the photoresist material which results in a reduced incidence of these Blob Defects consists of using a Puddle Development technique to develop the photoresist material, and subsequently exposing the semiconductor wafer to at least one Puddle Rinse cycle which uses water.

    Abstract translation: 在可用的深紫外（DUV）敏感光刻胶的曝光和显影中，已经观察到遵循现有技术的标准曝光和显影方法导致残留的光致抗蚀剂材料的各种组分的不希望的残留物（表示为Blob缺陷）的高密度 在半导体基板（主体）上。 曝光和显影光致抗蚀剂材料的方法导致这些Blob缺陷的发生率降低，包括使用水坑开发技术开发光致抗蚀剂材料，随后将半导体晶片暴露于使用水的至少一个水坑冲洗循环。

    ONE-STEP ETCH PROCESSES FOR DUAL DAMASCENE METALLIZATION
    6.
    发明申请
    ONE-STEP ETCH PROCESSES FOR DUAL DAMASCENE METALLIZATION 审中-公开
    用于双重金属化的一步蚀刻工艺

    公开(公告)号：WO0229887A3

    公开(公告)日：2003-02-06

    申请号：PCT/US0126998

    申请日：2001-08-30

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： LU ZHIJIAN ,  NING XIAN J ,  YIN XIAOMING

    IPC: H01L21/768

    CPC classification number: H01L21/76811 ,  H01L21/76813

    Abstract: A method for forming a dual damascene structure, employs the steps of forming a dielectric layer (14), patterning a first resist layer (16) on the dielectric layer to form a via pattern (26) and patterning a second resist layer (28) to form a line pattern (38) in communication with the via pattern formed on the first resist layer wherein the first resist layer includes exposed portions adjacent to the via pattern. The first resist layer, the second resist layer and the dielectric layer are etched such that the dielectric layer has a via (40) formed therein which gets deeper during the etching process. The dielectric layer has a trench (42) formed therein in communication with the via which gets deeper after the exposed portions of the first resist layer are consumed by the etching process.

    Abstract translation: 一种用于形成双镶嵌结构的方法，采用以下步骤：形成电介质层（14），图案化介电层上的第一抗蚀剂层（16）以形成通孔图案（26）并使第二抗蚀剂层（28）构图， 以形成与形成在第一抗蚀剂层上的通孔图案相连的线图案，其中第一抗蚀剂层包括与通孔图案相邻的暴露部分。 蚀刻第一抗蚀剂层，第二抗蚀剂层和电介质层，使得介电层具有在其中形成的通孔（40），其在蚀刻工艺期间变深。 电介质层具有形成在其中的与通孔连通的沟槽（42），其在通过蚀刻工艺消耗第一抗蚀剂层的暴露部分之后变深。

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