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    INTERCONNECTION FOR ACCOMODATING THERMAL EXPANSION FOR LOW ELASTIC MODULUS DIELECTRICS
    1.
    发明申请
    INTERCONNECTION FOR ACCOMODATING THERMAL EXPANSION FOR LOW ELASTIC MODULUS DIELECTRICS 审中-公开
    用于低温弹性模拟电容的热膨胀的互连

    公开(公告)号：WO0201632A3

    公开(公告)日：2003-10-23

    申请号：PCT/US0120354

    申请日：2001-06-27

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： MATUSIEWICZ GERALD ,  BRASE GABRIELA

    IPC: H01L23/12 ,  H01L23/528 ,  H01L23/522 ,  H01L23/31

    CPC classification number: H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Damage to interconnect structures including vias and/or device interconnects through insulators having a low modulus of elasticity between materials having different coefficients of thermal expansion (CTEs) by providing bends or jogs in an interconnect which limit the axial length of the interconnect adjacent the via or device contact in accordance with the difference in CTEs. The interconnect thus limits the development of shear forces and serves to relieve them by flexure of the interconnect across portions of the narrow width of the interconnect; preventing concentration of shear forces near the via or device contact. Implementation as a design rule based on limitation of length of a straight segment of an interconnect trace is preferred.

    Abstract translation: 通过在互连中提供弯曲或点动来限制邻近通孔的互连的轴向长度，从而损坏互连结构，包括通孔和/或器件互连通过具有不同热膨胀系数（CTE）的材料之间具有低弹性模量的绝缘体，或 设备接触符合CTE的不同。 因此，互连限制了剪切力的发展，并且用于通过互连件在互连的窄宽度的部分上的挠曲来缓解它们; 防止通孔或器件接触附近的剪切力集中。 作为基于互连迹线的直线段的长度的限制的设计规则的实现是优选的。

    SOLID-STATE CIRCUIT ASSEMBLY
    2.
    发明申请
    SOLID-STATE CIRCUIT ASSEMBLY 审中-公开
    半导体电路

    公开(公告)号：WO2004053995A2

    公开(公告)日：2004-06-24

    申请号：PCT/DE0303934

    申请日：2003-11-27

    Applicant: INFINEON TECHNOLOGIES AG ,  BRASE GABRIELA ,  OSTERMAYR MARTIN ,  RUDERER ERWIN

    Inventor： BRASE GABRIELA ,  OSTERMAYR MARTIN ,  RUDERER ERWIN

    IPC: H01L21/768 ,  H01L29/06 ,  H01L29/417

    CPC classification number: H01L29/417 ,  H01L21/7684 ,  H01L29/0615

    Abstract: The invention relates to a solid-state circuit assembly comprising a semiconductor substrate (1), a first doping area, a second doping area (2), a connection doping area (3), an insulating layer (6) and a planarised conductive structure (4, 5). A discharge doping area (7) which is formed in the first and second doping areas (1, 2) makes it possible to reliably remove charge carriers which are produced during planarisation, thereby avoiding a dendrite formation.

    Abstract translation: 本发明涉及一种半导体集成电路器件，包括在半导体基板（1），第一掺杂区，第二掺杂区（2），连接掺杂区（3），绝缘层（6）和一对被平坦化导电结构（4，5），其特征在于 通过在第一和第二掺杂区域（1,2）中形成的电荷掺杂区域（7），平坦化期间形成的电荷载流子可以可靠地消散并防止枝晶形成。

    3.
    发明专利
    未知

    公开(公告)号：DE19937994A1

    公开(公告)日：2001-02-22

    申请号：DE19937994

    申请日：1999-08-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRASE GABRIELA ,  GRANDEMY GREGOIRE

    IPC: H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/283

    Abstract: The invention relates to an etching process for dual-layer metallisation, or dual damascene structuring, which is simple and economical and which reliably prevents fences from forming in the area of the polymer intermediate layer during the etching process. To this end, the invention provides that the oxide layer and the polymer intermediate layer are etched for the dual damascene structuring using a CF4 ARC open process, with a high degree of selectivity in relation to the photoresist and with a longer etching time.

    6.
    发明专利
    未知

    公开(公告)号：DE19937994C2

    公开(公告)日：2003-12-11

    申请号：DE19937994

    申请日：1999-08-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRASE GABRIELA ,  GRANDEMY GREGOIRE

    IPC: H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/283

    Abstract: The novel etching process for a two-layer metallization, or dual damascene patterning, is simple and cost-effective to carry out and reliably prevents fences from forming during the etching process in the region of the polymer intermediate layer. The etching of the oxide layer and of the polymer intermediate layer for the dual damascene patterning is effected by a CF4 ARC open process with high selectivity with respect to the photoresist with a lengthened etching time.

    Chiprandversiegelung
    7.
    发明专利
    Chiprandversiegelung 未知

    公开(公告)号：DE102012018611B3

    公开(公告)日：2013-10-24

    申请号：DE102012018611

    申请日：2012-09-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRASE GABRIELA ,  NELLE PETER ,  SCHINDLER GUENTHER ,  ZUNDEL MARKUS

    IPC: H01L29/06 ,  H01L21/76 ,  H01L29/78

    Abstract: Die Beschreibung bezieht sich auf Halbleiterbauelement mit einem Halbleiterkörper, einer Isolation an dem Halbleiterkörper und einem Zellenfeld, welches zumindest teilweise in dem Halbeleiterkörper angeordnet ist. Das Zellenfeld weist zumindest einen p-n Übergang und zumindest eine Kontaktierung auf. Die Isolation ist in lateraler Richtung des Halbleiterkörpers von einer umlaufenden Diffusionsbarriere begrenzt. Die Diffusionsbarriere umfasst einen Graben, welcher die Isolation durchschneidet und in den Zellenbereich der Isolation und eine Randisolation teilt.

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