公开(公告)号：JP2001237393A

公开(公告)日：2001-08-31

申请号：JP2000399178

申请日：2000-12-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  SCHINDLER GUENTHER DR ,  KASTNER MARCUS ,  DEHM CHRISTINE

IPC: H01L21/316 ,  H01L21/02 ,  H01L21/318 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a ferroelectric memory. SOLUTION: A switching resistor (2) is formed on a semiconductor substrate (1), an isolation layer (4) is deposited on the switching transistor (2), and then a memory capacitor provided with a lower electrode (7) formed of platinum and a ferroelectric or paraelectric (8) is formed on the isolation layer. In order to protect the dielectric against intrusion of hydrogen in following manufacturing processes, a first barrier layer (5) is embedded in the isolation layer (4) and, after formation of the memory capacity, a second barrier layer (10) connected to the first barrier layer (5) is deposited.

公开(公告)号：WO02054494A3

公开(公告)日：2003-02-13

申请号：PCT/DE0104767

申请日：2001-12-14

Applicant: INFINEON TECHNOLOGIES AG ,  KASTNER MARCUS ,  MIKOLAJICK THOMAS

Inventor： KASTNER MARCUS ,  MIKOLAJICK THOMAS

IPC: H01L21/8242 ,  H01L21/8246 ,  H01L27/06 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115

CPC classification number: H01L27/108 ,  H01L27/0694 ,  H01L27/10808 ,  H01L27/1082 ,  H01L27/10835 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10858 ,  H01L27/10861 ,  H01L27/11502 ,  H01L27/11507 ,  Y10S438/928

Abstract: The invention relates to a method for producing an integrated semiconductor memory arrangement. According to said method, two capacitor modules (10, 20) are formed for each selection transistor (8) from the front and rear side of the substrate wafer (1) respectively. Said inventive process achieves a higher packing density of memory cells by the utilisation of the rear side of the wafer. A twofold memory read signal can be used for the same cell surface area. Conditions in addition to "0" or "1" can also be saved for each selection transistor (8) in a ferroelectric memory arrangement, if the two capacitor modules have a different structure in terms of layer thickness, surface area or material.

Abstract translation: 在制造集成半导体存储器结构，每个选择晶体管（8）的本发明方法具有形成在从前面和（1）前衬底晶片的背面每两个电容器模块（10，20）。 通过利用该晶片背面上的更高的填充密度为所提出的处理流程可以通过存储单元来实现。 具有相同小区区域可使用两次的读出信号。 此外，在强电介质存储器件中，当两个电容器模块相对于厚度，面积或每地址材料，即构成不同 每个选择晶体管（8）可为“0”或“1”被存储更多的状态。

公开(公告)号：DE10022656A1

公开(公告)日：2001-11-08

申请号：DE10022656

申请日：2000-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  AHLSTEDT MATTIAS ,  SCHINDLER GUENTHER ,  KASTNER MARCUS ,  BEITEL GERHARD ,  WEINRICH VOLKER

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/8246 ,  H01L27/108 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/8242

Abstract: Removing structures from a substrate comprises preparing a substrate with the structures to be removed; applying a sacrificial layer; and removing the structures and the sacrificial layer by polishing. An Independent claim is also included for a process for removing one or more structured layers from a substrate. Preferred Features: The structures are made from a precious metal, especially Pt or Ir, an oxide of a precious metal, a dielectric material or a ferroelectric material. The sacrificial layer is a silicon oxide or silicon nitride layer.

公开(公告)号：DE102008051467A1

公开(公告)日：2009-05-07

申请号：DE102008051467

申请日：2008-10-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MEYER THORSTEN ,  BRUNNBAUER MARKUS ,  KASTNER MARCUS ,  BRADL STEPHAN

IPC: H01L25/16 ,  H01L23/28 ,  H01L23/34

Abstract: A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first material. A coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material.

公开(公告)号：DE10000005C1

公开(公告)日：2001-09-13

申请号：DE10000005

申请日：2000-01-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KASTNER MARCUS ,  SCHINDLER GUENTHER ,  HARTNER WALTER ,  DEHM CHRISTINE

IPC: H01L21/316 ,  H01L21/02 ,  H01L21/318 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L21/8239

Abstract: A switching transistor (2) is formed on a semiconductor substrate (1). An insulating layer (4) is applied, with a first layer (5) preventing hydrogen ingress. A memory condenser coupled with the transistor is added. It includes a lower (7) and upper electrode (9), with intervening metal oxide-containing layer (8). In a vertical etching stage, the insulation layer outside the storage condenser is removed to a set depth, laying bare the first barrier layer. On the storage condenser, insulating layer and first barrier layer, a second barrier layer (10) is applied, especially blocking hydrogen ingress. Preferred etching methods and materials employed are claimed.

公开(公告)号：DE10022656B4

公开(公告)日：2006-07-06

申请号：DE10022656

申请日：2000-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  AHLSTEDT MATTIAS ,  SCHINDLER GUENTHER ,  KASTNER MARCUS ,  BEITEL GERHARD ,  WEINRICH VOLKER

IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108

Abstract: A method for removing structures from a substrate is described. The method includes providing a substrate that has the structures that must be removed, applying a sacrifice layer, and removing the structures and the sacrifice layer in a polishing step. The method has the advantage that the sacrifice layer surrounds the structures that must be removed and stabilizes them, so that the structures can be eroded slowly and successively in the subsequent polishing step without breaking off. This prevents a smearing of the material of the structures such as occurs given direct polishing without a sacrifice layer.

公开(公告)号：DE10001118A1

公开(公告)日：2001-07-26

申请号：DE10001118

申请日：2000-01-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  SCHINDLER GUENTHER ,  KASTNER MARCUS

IPC: H01L21/8242 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/108

Abstract: Production of a semiconductor component involves forming switching transistor (2) on semiconductor substrate, applying a first insulating layer (4) to the transistor, applying a storage capacitor (3) containing a lower (31) and an upper electrode (33a) and a metal oxide -containing layer to the insulating layer, and applying a second insulating layer (5) to the capacitor. The electrodes contain a platinum metal or a conducting oxide of a platinum metal. A conducting protective layer (33b) is applied to the upper electrode in a contact opening (51) which is filled with tungsten by chemical vapor deposition in a hydrogen atmosphere. Preferred Features: The electrodes contain platinum or consist of platinum. The metal oxide-containing layer is made of SrBi2(Ta, Nb)2O9, Pb(ZrTi)O3 or Bi4Ti3O12. The protective layer is made of WSi, IrOx, RhOx, RuOx, OsOx, SrRuO3, LaSrCoOx, a high temperature superconductor or carbide.