公开(公告)号：DE10043215C1

公开(公告)日：2002-04-18

申请号：DE10043215

申请日：2000-09-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHR MATTHIAS UWE ,  POLEI VERONIKA ,  SPERL IRENE ,  SCHILLING UWE

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/525 ,  H01L21/768

Abstract: A method for producing antifuse structures and antifuses by which adjacent conductive regions can be selectively electrically connected involve the application of a sacrificial layer to a first conductive region. The sacrificial layer is patterned with the aid of a photolithographic method. A fuse layer is applied and the sacrificial layer is then removed. A non-conductive layer is applied and a conductive material is introduced in an opening in the non-conductive layer for the purpose of forming a second conductive region.

公开(公告)号：DE10032795A1

公开(公告)日：2002-01-24

申请号：DE10032795

申请日：2000-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHILLING UWE

IPC: H01L21/316 ,  H01L21/8242

Abstract: Semiconductor element comprises a substrate (1) with trenches (15) whose walls are lined with a layer (10) of insulating material. A liner layer (8) made of insulating material and applied by a plasma process is arranged below the layer (10) of insulating material. An Independent claim is also included for a process for the production of a semiconductor element comprising providing trenches in a substrate, depositing a liner layer, providing a layer of insulating material using a deposition process, and anisotropically etching the layer of insulating material to remove it from the base of the trenches. Preferred Features: The substrate is made of silicon and the insulating material is made of silicon dioxide. The layer of insulating material is applied by an ozone-TEOS process. A nitride layer (5) is formed on the surface of the substrate and is partially covered with the liner layer.

公开(公告)号：DE10032795C2

公开(公告)日：2002-06-13

申请号：DE10032795

申请日：2000-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHILLING UWE

IPC: H01L21/316 ,  H01L21/8242

Abstract: A process for fabricating a semiconductor component includes providing a trench in a substrate and depositing a liner layer on the resulting structure using a nonconformal deposition process. This results in the liner layer being significantly smaller at the trench walls and base than on the substrate surface. An insulating layer is provided on the resulting structure by a conformal deposition process. The insulating layer is then anisotropically etched to remove the insulating layer from a region of the trench base.

公开(公告)号：DE19944740A1

公开(公告)日：2001-04-19

申请号：DE19944740

申请日：1999-09-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KIRCHHOFF MARKUS ,  SPERLICH HANS-PETER ,  SCHILLING UWE ,  GABRIC ZVONIMIR ,  SPINDLER OSWALD ,  WEGE STEPHAN ,  GLAWISCHNIG HANS

IPC: H01L21/316 ,  H01L21/318 ,  H01L21/762 ,  H01L21/768

Abstract: Shrinkage-free filling of trenches in integrated circuits comprises applying a layer of selectively growing material on a growth-promoting layer and a growth-halting layer (2) so bumps (3) are formed which are covered laterally by the growth-halting layer before applying the layer of selectively growing material. After the growth-halting layer is applied, the growth-promoting layer is produced on surfaces parallel to the substrate (4) by an isotropic treatment and then removed on the surfaces that are parallel to the bumps. Preferred Features: The growth-promoting layer is removed on the parallel surfaces on the bumps by chemical-mechanical polishing. The growth-promoting layer is produced by an oxygen plasma.

公开(公告)号：DE10202140A1

公开(公告)日：2003-08-07

申请号：DE10202140

申请日：2002-01-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  TEMMLER DIETMAR ,  SCHUPKE KRISTIN ,  SCHILLING UWE

IPC: H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  B81C1/00

Abstract: A semiconductor component having a cavity is produced by: (i) forming a cavity in a monocrystalline silicon substrate (1), and covering walls of the cavity with a cover layer at least in an upper end region of the cavity; (ii) depositing a covering layer on the silicon substrate with a selective epitaxial process; and (iiii) growing the covering layer only on the silicon surface. Production of a semiconductor component having a cavity comprises: (a) providing a monocrystalline silicon substrate having a silicon surface; (b) forming a cavity in the silicon substrate and covering walls of the cavity, with a cover layer at least in an upper end region of the cavity; (c) depositing a covering layer on the silicon substrate with a selective epitaxial process; and (d) growing the covering layer only on the silicon surface to cover the cavity with the covering layer, and to form a covered cavity in the monocrystalline silicon substrate.

公开(公告)号：DE19944740C2

公开(公告)日：2001-10-25

申请号：DE19944740

申请日：1999-09-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KIRCHHOFF MARKUS ,  SPERLICH HANS-PETER ,  SCHILLING UWE ,  GABRIC ZVONIMIR ,  SPINDLER OSWALD ,  WEGE STEPHAN ,  GLAWISCHNIG HANS

IPC: H01L21/316 ,  H01L21/318 ,  H01L21/762 ,  H01L21/314 ,  H01L21/768

Abstract: A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.