公开(公告)号：JP2001273761A

公开(公告)日：2001-10-05

申请号：JP2001037522

申请日：2001-02-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BACHHOFER HARALD ,  HANEDER THOMAS PETER ,  ULLMANN MARC ,  BRAUN GEORG ,  HONLEIN WOLFGANG

IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To prevent a present state from being changed to a polarization state in which other ferroelectrioc transistor in other memory cell in a memory matrix cannot be discriminated, when a state is read out from a ferroelectric transistor or a state is stored in the ferroelectric transistor. SOLUTION: Threshold voltage of an other ferroelectric transistor in a memory matrix is increased by applying drain-substrate voltage to a ferroelectric transistor, when a state is read out from a ferroelectric transistor or a state is stored in the ferroelectric transistor.

公开(公告)号：WO0250842A3

公开(公告)日：2002-12-27

申请号：PCT/DE0104785

申请日：2001-12-19

Applicant: INFINEON TECHNOLOGIES AG ,  GOEBEL HOLGER ,  HOENIGSCHMID HEINZ ,  HOENLEIN WOLFGANG ,  HANEDER THOMAS ,  ULLMANN MARC

Inventor： GOEBEL HOLGER ,  HOENIGSCHMID HEINZ ,  HOENLEIN WOLFGANG ,  HANEDER THOMAS ,  ULLMANN MARC

IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C11/22 ,  Y10S977/943

Abstract: The status is read out from or stored in the ferroelectrical transistor. During the reading out or storing of the status, at least one further ferroelectrical transistor in the memory matrix is controlled such as to be operated in the depletion region thereof.

Abstract translation: 该状态从铁电晶体管读出或存储在铁电晶体管中。 在读取或存储状态期间，存储器矩阵中的至少一个另外的铁电晶体管被驱动，使得其在其耗尽区中操作。

公开(公告)号：DE50001170D1

公开(公告)日：2003-03-06

申请号：DE50001170

申请日：2000-03-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  ULLMANN MARC

IPC: G11C11/22

Abstract: An integrated memory has word lines that run in a first direction, and bit lines and control lines that run in a second direction, which is perpendicular to the first direction. A controllable path of each memory transistor connects one of the bit lines to one of the control lines. The control electrode of each memory transistor is connected to one of the word lines. Since the bit lines and control lines run in the same direction and are thus arranged parallel to one another, they can be arranged within a common wiring plane of the integrated memory. Since the terminals of the controllable path are usually likewise arranged in a common wiring plane, for example in a substrate of the integrated memory, it is possible, to arrange the bit lines and control lines in the same wiring plane as the controllable path of the transistors.

公开(公告)号：DE19913571C2

公开(公告)日：2002-11-07

申请号：DE19913571

申请日：1999-03-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  ULLMANN MARC

IPC: G11C11/22

Abstract: An integrated memory has word lines that run in a first direction, and bit lines and control lines that run in a second direction, which is perpendicular to the first direction. A controllable path of each memory transistor connects one of the bit lines to one of the control lines. The control electrode of each memory transistor is connected to one of the word lines. Since the bit lines and control lines run in the same direction and are thus arranged parallel to one another, they can be arranged within a common wiring plane of the integrated memory. Since the terminals of the controllable path are usually likewise arranged in a common wiring plane, for example in a substrate of the integrated memory, it is possible, to arrange the bit lines and control lines in the same wiring plane as the controllable path of the transistors.

公开(公告)号：DE50112892D1

公开(公告)日：2007-10-04

申请号：DE50112892

申请日：2001-02-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BACHHOFER HARALD ,  BRAUN GEORG ,  HANEDER THOMAS PETER ,  HOENLEIN WOLFGANG DR ,  ULLMANN MARC

IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

Abstract: The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.

公开(公告)号：DE50104250D1

公开(公告)日：2004-11-25

申请号：DE50104250

申请日：2001-12-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL HOLGER ,  HOENIGSCHMID HEINZ ,  HOENLEIN WOLFGANG ,  HANEDER THOMAS ,  ULLMANN MARC

IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

Abstract: The state is read out from the ferroelectric transistor or stored in the ferroelectric transistor. During the read-out or storage of the state, at least one further ferroelectric transistor in the memory matrix is driven in such a way that it is operated in its depletion region.

公开(公告)号：DE10064031A1

公开(公告)日：2002-07-18

申请号：DE10064031

申请日：2000-12-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ULLMANN MARC ,  HANEDER THOMAS ,  HOENIGSCHMID HEINZ ,  GOEBEL HOLGER ,  HOENLEIN WOLFGANG

IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

Abstract: The state is read out from the ferroelectric transistor or stored in the ferroelectric transistor. During the read-out or storage of the state, at least one further ferroelectric transistor in the memory matrix is driven in such a way that it is operated in its depletion region.