公开(公告)号：WO2003028099A2

公开(公告)日：2003-04-03

申请号：PCT/US2002/025312

申请日：2002-08-08

Applicant: INTEL CORPORATION

Inventor： MCCORMICK, Carolyn ,  JESSEP, Rebecca ,  DUNGAN, John ,  BOGGS, David ,  SATO, Daryl

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H05K1/113 ,  H05K1/114 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/10734 ,  H05K2203/1394 ,  H01L2224/05599

Abstract: An arrangement of pads with selective via in pad for mounting a semiconductor package on a substrate. In order to strengthen the soldered bonds, standard pads, which have a stronger bond, are used in locations of greatest stress and deflection. Vias in pad (VIP) are used at all other locations to improve routing advantages due to their smaller surface area.

Abstract translation: 具有用于将半导体封装安装在衬底上的用于衬垫中的选择性通孔的焊盘布置。 为了加强焊接接头，具有较强粘结性的标准焊盘用于最大应力和偏转的位置。 所有其他位置都使用垫（VIP）中的通孔，以提高路由优势，因为它们的表面积较小。

公开(公告)号：WO2003028413A1

公开(公告)日：2003-04-03

申请号：PCT/US2002/025077

申请日：2002-08-07

Applicant: INTEL CORPORATION

Inventor： BOGGS, David ,  JESSEP, Rebecca ,  MCCORMICK, Carolyn ,  SATO, Daryl ,  DUNGAN, John

IPC: H05K1/02

CPC classification number: H05K1/0269 ,  H05K3/3452 ,  H05K2201/09063 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/099 ,  H05K2203/163 ,  H05K2203/166 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T428/218 ,  Y10T428/24273 ,  Y10T428/24917

Abstract: A registration coupon (20) is provided for a printed circuit board or other substrate. The registration coupon (20) may be used to determine a hole-to-outer layer feature registration and a solder mask registration. The registration coupon (20) may include a registration hole (30) provided on the circuit board, a metal pad (60) and an anti-pad (40) provided on the circuit board about the registration hole (30), and a solder mask (70) covering the metal pad (60).

Abstract translation: 为印刷电路板或其他基板提供了注册券（20）。 注册券（20）可以用于确定空穴到外层特征对准和焊接掩模配准。 注册券（20）可以包括设置在电路板上的注册孔（30），设置在电路板上的金属垫（60）和防焊垫（40），其围绕配准孔（30），以及焊料 掩模（70）覆盖金属垫（60）。

公开(公告)号：WO2003028414A1

公开(公告)日：2003-04-03

申请号：PCT/US2002/031332

申请日：2002-09-30

Applicant: INTEL CORPORATION

Inventor： MCCORMICK, Carolyn ,  SATO, Daryl ,  BOGGS, David ,  JESSUP, Rebecca ,  DUNGAN, John

IPC: H05K1/11

CPC classification number: H05K3/3436 ,  H01L2924/15151 ,  H05K1/113 ,  H05K1/116 ,  H05K3/0094 ,  H05K2201/09381 ,  H05K2201/0959 ,  H05K2201/09663 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2203/0455 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613

Abstract: An apparatus that includes a substrate, one or more via in pads (202) in the substrate; and one or more vents (204) in at least one of the one or more via in pads (202).

Abstract translation: 一种包括衬底的装置，在衬底中的衬垫（202）中的一个或多个通孔; 和在衬垫（202）中的一个或多个通孔中的至少一个中的一个或多个通气口（204）。

公开(公告)号：WO2003107726A1

公开(公告)日：2003-12-24

申请号：PCT/US2003/015275

申请日：2003-05-16

Applicant: INTEL CORPORATION

Inventor： BOGGS, David ,  SATO, Daryl ,  DUNGAN, John ,  PAEK, Gary

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K3/4644 ,  H05K2201/09245 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/09645 ,  H05K2201/09827 ,  Y10T29/49126

Abstract: An electronic assembly (10) is disclosed. The electronic assembly (10) includes a lower portion (28) and a first elongate trace (32) formed on an upper surface of the lower portion (28). The trace (32) is covered by an upper portion (26), and an opening (18) formed through an upper surface of the upper portion (26) extends to the trace (32) to expose a portion of the trace (32). A second elongate trace (20) is formed on the upper portion (26). A portion of the second elongate trace (20) positioned in the opening (18) formed through the upper surface of the upper portion (26) contacts the first elongate trace (32) through the opening (18) to form an electrical interconnection (46) between the first trace (32) and the second trace (20).

Abstract translation: 公开了一种电子组件（10）。 电子组件（10）包括下部（28）和形成在下部（28）的上表面上的第一细长迹线（32）。 迹线（32）被上部（26）覆盖，并且通过上部（26）的上表面形成的开口（18）延伸到迹线（32）以暴露迹线（32）的一部分， 。 第二细长迹线（20）形成在上部（26）上。 定位在通过上部（26）的上表面形成的开口（18）中的第二细长迹线（20）的一部分通过开口（18）接触第一细长迹线（32）以形成电互连 ）在第一迹线（32）和第二迹线（20）之间。

公开(公告)号：EP1430756A1

公开(公告)日：2004-06-23

申请号：EP02773693.3

申请日：2002-09-30

Applicant: INTEL CORPORATION

Inventor： MCCORMICK, Carolyn ,  SATO, Daryl ,  BOGGS, David ,  JESSUP, Rebecca ,  DUNGAN, John

IPC: H05K1/11 ,  H05K3/34

CPC classification number: H05K3/3436 ,  H01L2924/15151 ,  H05K1/113 ,  H05K1/116 ,  H05K3/0094 ,  H05K2201/09381 ,  H05K2201/0959 ,  H05K2201/09663 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2203/0455 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613

Abstract: An apparatus that includes a substrate, one or more via in pads (202) in the substrate; and one or more vents (204) in at least one of the one or more via in pads (202).

公开(公告)号：EP1430755A1

公开(公告)日：2004-06-23

申请号：EP02799370.8

申请日：2002-08-07

Applicant: INTEL CORPORATION

Inventor： BOGGS, David ,  JESSEP, Rebecca ,  MCCORMICK, Carolyn ,  SATO, Daryl ,  DUNGAN, John

IPC: H05K1/02

CPC classification number: H05K1/0269 ,  H05K3/3452 ,  H05K2201/09063 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/099 ,  H05K2203/163 ,  H05K2203/166 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T428/218 ,  Y10T428/24273 ,  Y10T428/24917

Abstract: A registration coupon (20) is provided for a printed circuit board or other substrate. The registration coupon (20) may be used to determine a hole-to-outer layer feature registration and a solder mask registration. The registration coupon (20) may include a registration hole (30) provided on the circuit board, a metal pad (60) and an anti-pad (40) provided on the circuit board about the registration hole (30), and a solder mask (70) covering the metal pad (60).

公开(公告)号：EP1430531A2

公开(公告)日：2004-06-23

申请号：EP02752766.2

申请日：2002-08-08

Applicant: INTEL CORPORATION

Inventor： MCCORMICK, Carolyn ,  JESSEP, Rebecca ,  DUNGAN, John ,  BOGGS, David ,  SATO, Daryl

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H05K1/113 ,  H05K1/114 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/10734 ,  H05K2203/1394 ,  H01L2224/05599

Abstract: An arrangement of pads with selective via in pad for mounting a semiconductor package on a substrate. In order to strengthen the soldered bonds, standard pads, which have a stronger bond, are used in locations of greatest stress and deflection. Vias in pad (VIP) are used at all other locations to improve routing advantages due to their smaller surface area.