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公开(公告)号：US20230271825A1
公开(公告)日：2023-08-31
申请号：US17923648
申请日：2020-06-28
Inventor： Quanshui ZHENG , Xiaojian XIANG
CPC classification number: B81C1/00357 , B81B7/02 , B81B2201/038 , B81B2203/04 , B81C2201/0102 , B81C2201/0132 , B81C2201/014 , B81C2203/032 , B81C2203/0136 , B81C2201/0181
Abstract: Provided is an atomic-smooth device with a microstructure. The device includes, from the bottom to top, a substrate, a bonding material, a second dielectric layer on the substrate, the microstructure, and a first dielectric layer, where a surface of the first dielectric layer is an atomic-smooth surface. Further provided is a method for preparing an atomic-smooth device with a microstructure to effectively avoid pits or burrs generated when the existing microstructure is machined.
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公开(公告)号：US11667517B2
公开(公告)日：2023-06-06
申请号：US16908243
申请日：2020-06-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Chia Liu , Chia-Hua Chu , Chun-Wen Cheng
CPC classification number: B81B7/0006 , B81B7/0051 , B81C1/00246 , B81B2201/0257 , B81B2201/0264 , B81B2201/0271 , B81C2201/0132 , B81C2201/0133 , B81C2201/0176 , B81C2201/0181 , B81C2201/112 , B81C2203/0714 , B81C2203/0735
Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
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公开(公告)号：US11644435B2
公开(公告)日：2023-05-09
申请号：US16845565
申请日：2020-04-10
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： ShuaiGang Xiao , David S. Kuo , Xiaomin Yang , Kim Yang Lee , Yautzong Hsu , Michael R. Feldbaum
IPC: G01R27/08 , G01N27/327 , G01N33/487 , C12Q1/6869 , C23C14/00 , B01L3/00 , G01N27/414 , G01N27/447 , B82Y5/00
CPC classification number: G01N27/3278 , B01L3/502707 , B01L3/502715 , B01L3/502761 , C12Q1/6869 , C23C14/00 , G01N27/4145 , G01N27/4146 , G01N27/44791 , G01N33/48721 , B81C2201/0143 , B81C2201/0176 , B81C2201/0181 , B82Y5/00
Abstract: A DNA sequencing device and methods of making. The device includes a pair of electrodes having a spacing of no greater than about 2 nm, the electrodes being exposed within a nanopore to measure a DNA strand passing through the nanopore. The device can be made by depositing a conductive layer over a sacrificial channel and then removing the sacrificial channel to form the electrode gap.
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公开(公告)号：US20180369809A1
公开(公告)日：2018-12-27
申请号：US15630982
申请日：2017-06-23
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Emmanuel Delamarche , Onur Gökçe
CPC classification number: B01L3/502707 , B01J2219/00997 , B01L3/502715 , B01L3/502738 , B01L3/502769 , B01L2200/12 , B01L2300/0816 , B01L2300/0874 , B01L2300/0887 , B01L2400/0406 , B01L2400/0688 , B01L2400/086 , B81B1/00 , B81B7/0093 , B81B2201/051 , B81B2201/058 , B81C99/006 , B81C2201/0181
Abstract: The invention is directed to a microfluidic device, which comprises distinct, parallel levels, including a first level and a second level. It further includes: a first microchannel, a second microchannel, and a node. This node comprises: an inlet port, a cavity, a via, and an outlet port. The cavity is formed on the first level and is open on a top side. The inlet port is defined on the first level; it branches from the first microchannel and communicates with the cavity through an ingress thereof. The outlet port, branches to the second microchannel on the second level. The via extends from the bottom side of the cavity, down to the outlet port, so the cavity may communicate with the outlet port. In addition, the cavity comprises a liquid blocking element to prevent an aqueous liquid filling the inlet port to reach the outlet port.
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公开(公告)号：US10081533B2
公开(公告)日：2018-09-25
申请号：US14448767
申请日：2014-07-31
Applicant: Infineon Technologies AG
Inventor： Ulrich Schmid , Tobias Frischmuth , Peter Irsigler , Thomas Grille , Daniel Maurer , Ursula Hedenig , Markus Kahn , Günter Denifl
IPC: B81B3/00 , B06B1/02 , B81C1/00 , H04R19/02 , H04R19/04 , H04R31/00 , H04R7/24 , H04R7/02 , H04R19/00
CPC classification number: B81B3/0021 , B06B1/02 , B81B3/007 , B81B2201/0257 , B81B2201/0264 , B81B2203/0109 , B81B2203/0118 , B81B2203/0127 , B81B2203/051 , B81C1/00142 , B81C1/0015 , B81C1/00158 , B81C1/00373 , B81C2201/0176 , B81C2201/0181 , B81C2201/019 , H04R7/02 , H04R7/24 , H04R19/005 , H04R19/02 , H04R19/04 , H04R31/00 , H04R31/003 , H04R2201/003 , H04R2307/023 , H04R2400/01 , H04R2499/11
Abstract: A micromechanical structure includes a substrate and a functional structure arranged at the substrate. The functional structure has a functional region configured to deflect with respect to the substrate responsive to a force acting on the functional region. The functional structure includes a conductive base layer and a functional structure comprising a stiffening structure having a stiffening structure material arranged at the conductive base layer and only partially covering the conductive base layer at the functional region. The stiffening structure material includes a silicon material and at least a carbon material.
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Patent Agency Ranking
公开(公告)号：US20180174851A1
公开(公告)日：2018-06-21
申请号：US15890465
申请日：2018-02-07
Inventor： Robert W. Carpick , Frank Streller , Rahul Agarwal , Filippo Mangolini
CPC classification number: H01L21/28518 , B81B3/0086 , B81B2201/01 , B81B2203/04 , B81C1/00698 , B81C2201/0181 , C01B33/06 , H01L29/456 , H01L29/84
Abstract: The disclosed subject matter provides thin films including a metal silicide and methods for forming such films. The disclosed subject matter can provide techniques for tailoring the electronic structure of metal thin films to produce desirable properties. In example embodiments, the metal silicide can comprise a platinum silicide, such as for example, PtSi, Pt2Si, or Pt3Si. For example, the disclosed subject matter provides methods which include identifying a desired phase of a metal silicide, providing a substrate, depositing at least two film layers on the substrate which include a first layer including amorphous silicon and a second layer including metal contacting the first layer, and annealing the two film layers to form a metal silicide. Methods can be at least one of a source-limited method and a kinetically-limited method. The film layers can be deposited on the substrate using techniques known in the art including, for example, sputter depositing.
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公开(公告)号：US09988263B2
公开(公告)日：2018-06-05
申请号：US14914215
申请日：2013-08-30
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Patrick Wayne Sadik , Roger A. McKay
IPC: H01L21/306 , B81C1/00 , B41J2/16
CPC classification number: B81C1/00063 , B41J2/162 , B41J2/1626 , B81B2201/052 , B81C2201/0115 , B81C2201/0133 , B81C2201/0181
Abstract: An example provides a method including sputtering a metal catalyst onto a substrate, exposing the substrate to a solution that reacts with the metal catalyst to form a plurality of pores in the substrate, and etching the substrate to remove the plurality of pores to form a recess in the substrate.
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公开(公告)号：US09932222B2
公开(公告)日：2018-04-03
申请号：US15162994
申请日：2016-05-24
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Michael T. Brigham , Christopher V. Jahnes , Cameron E. Luce , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper , Eric J. White
CPC classification number: B81C1/0015 , B81B3/0021 , B81B2203/0118 , B81B2203/0315 , B81B2207/09 , B81C1/00047 , B81C1/00269 , B81C1/00365 , B81C1/00531 , B81C1/00936 , B81C2201/0104 , B81C2201/0107 , B81C2201/0121 , B81C2201/0125 , B81C2201/0132 , B81C2201/0176 , B81C2201/0181 , B81C2203/0109 , B81C2203/0145 , B81C2203/0714 , G06F17/5009
Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.
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公开(公告)号：US09752247B2
公开(公告)日：2017-09-05
申请号：US14017510
申请日：2013-09-04
Applicant: University of Southern California
Inventor： Adam L. Cohen
IPC: B81C1/00 , C25D5/10 , B33Y10/00 , C25D1/00 , C25D5/02 , C25D5/12 , H01L21/288 , H05K3/24 , C25D5/22
CPC classification number: C25D5/10 , B33Y10/00 , B33Y70/00 , B81C1/00126 , B81C2201/0181 , B81C2201/0197 , B81C2201/032 , C25D1/00 , C25D1/003 , C25D5/022 , C25D5/12 , C25D5/22 , C25D17/06 , H01L21/2885 , H05K3/241 , Y10T428/12486 , Y10T428/239
Abstract: An electroplating method that includes: a) contacting a first substrate with a first article, which includes a substrate and a conformable mask disposed in a pattern on the substrate; b) electroplating a first metal from a source of metal ions onto the first substrate in a first pattern, the first pattern corresponding to the complement of the conformable mask pattern; and c) removing the first article from the first substrate, is disclosed. Electroplating articles and electroplating apparatus are also disclosed.
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公开(公告)号：US09656855B1
公开(公告)日：2017-05-23
申请号：US15055072
申请日：2016-02-26
Inventor： Fu-Chun Huang , Li-Chen Yen , Tzu-Heng Wu , Yi-Heng Tsai , Chun-Ren Cheng
CPC classification number: B81B3/0086 , B81B3/0008 , B81B2203/0307 , B81B2207/015 , B81B2207/07 , B81C1/00246 , B81C2201/0132 , B81C2201/0181 , B81C2203/035
Abstract: A semiconductor structure includes a substrate, a dielectric layer disposed over the substrate, a sensing structure disposed over the dielectric layer, a bonding structure disposed over the dielectric layer, a conductive layer covering the sensing structure, and a barrier layer disposed over the dielectric layer, the conductive layer and the bonding structure, wherein the conductive layer and the bonding structure are at least partially exposed from the barrier layer.
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