公开(公告)号：US20230141467A1

公开(公告)日：2023-05-11

申请号：US17680267

申请日：2022-02-24

Applicant: Huazhong University of Science and Technology

Inventor： Weihua GUO ,  Xiangyang DAI ,  Qiaoyin LU

IPC: G02B6/13 ,  G02B6/122 ,  H05K1/14 ,  H05K3/36

CPC classification number: G02B6/13 ,  G02B6/1228 ,  H05K1/144 ,  H05K3/368 ,  H05K2201/041

Abstract: A hybrid integration method includes: assembling a motherboard chip, assembling a daughterboard chip, and assembling an integrated chip. The motherboard chip includes a motherboard chip body, a first metal region, a first vertical support assembly, and a first waveguide region arranged on the motherboard chip body, and the first waveguide region includes a first conventional waveguide region and a first coupling waveguide region used for vertical coupling which are fixedly connected to each other; the daughterboard chip includes a daughterboard chip body, a second metal region, a second vertical support assembly and a second waveguide region arranged on the daughterboard chip body, and the second waveguide region includes a second conventional waveguide region and a second coupling waveguide region used for vertical coupling which are fixedly connected to each other.

公开(公告)号：US20190250447A1

公开(公告)日：2019-08-15

申请号：US16269906

申请日：2019-02-07

Applicant: Japan Display Inc.

Inventor： Hideaki ABE ,  Yasuhito ARUGA ,  Hiroyuki ONODERA ,  Hiroki KATO ,  Yasushi NAKANO ,  Hitoshi KAWAGUCHI ,  Keisuke ASADA

IPC: G02F1/1345 ,  H05K1/02 ,  H05K1/14 ,  H05K1/11 ,  H05K1/18 ,  H05K3/36

CPC classification number: G02F1/13452 ,  G02F1/13458 ,  G02F1/1368 ,  G02F2001/133354 ,  G02F2202/28 ,  H01L27/1214 ,  H05K1/0266 ,  H05K1/11 ,  H05K1/144 ,  H05K1/181 ,  H05K3/368 ,  H05K2201/041 ,  H05K2201/049 ,  H05K2201/09936 ,  H05K2201/10136 ,  H05K2203/166

Abstract: A display device includes: a display panel including panel terminals; and a wiring substrate including first substrate terminals coupled to the panel terminals. The panel terminals include panel terminals arranged in a first region and panel terminals arranged in second regions sandwiching the first region. The first substrate terminals include first substrate terminals arranged in a third region and first substrate terminals arranged in fourth regions sandwiching the third region. A gap between panel terminals is substantially constant in the first and second regions. A first width of the panel terminals in the first region is different from a second width of the panel terminals in the second regions. A width of the first substrate terminals is substantially constant in the third and fourth regions. A first gap between first substrate terminals in the third region is different from a second gap between first substrate terminals in the fourth regions.

公开(公告)号：US20180279476A1

公开(公告)日：2018-09-27

申请号：US15916807

申请日：2018-03-09

Applicant: FUJITSU LIMITED

Inventor： Taiki UEMURA ,  Taiji SAKAI ,  Hideki KITADA

IPC: H05K1/14 ,  H05K1/11 ,  H05K3/32 ,  H05K3/40 ,  H05K1/18

CPC classification number: H05K1/145 ,  H01R12/712 ,  H05K1/115 ,  H05K1/14 ,  H05K1/144 ,  H05K1/181 ,  H05K3/0094 ,  H05K3/32 ,  H05K3/3436 ,  H05K3/4038 ,  H05K2201/041 ,  H05K2201/042 ,  H05K2201/09636 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/10515

Abstract: An electronic apparatus includes a first circuit board, a stacked circuit that is provided on the first circuit board through first coupling terminals and has a structure in which arithmetic elements and memory elements are stacked through inter-element coupling terminals and to which a signal is inputted from the first circuit board, and a second circuit board that is provided on the stacked circuit through second coupling terminals and to which a result of processing is outputted from the stacked circuit, wherein a number of the first coupling terminals and a number of the second coupling terminals are smaller than that of the inter-element coupling terminals.

公开(公告)号：US20180278034A1

公开(公告)日：2018-09-27

申请号：US15763513

申请日：2016-09-09

Applicant: AutoNetworks Technologies, Ltd. ,  Sumitomo Wiring Systems, Ltd. ,  SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Tou Chin ,  Arinobu Nakamura

IPC: H02G3/16 ,  H02G3/03 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  B60R16/023

CPC classification number: H02G3/16 ,  B60R16/0238 ,  H02G3/03 ,  H02G3/081 ,  H05K1/115 ,  H05K1/144 ,  H05K1/183 ,  H05K7/02 ,  H05K2201/041 ,  H05K2201/066 ,  H05K2201/10166 ,  H05K2201/10272 ,  H05K2201/10409

Abstract: A circuit assembly includes an electronic component including a plurality of terminals, a first board that is constituted by an insulating plate provided with a conductive path and an insertion hole into which the electronic component is inserted, a busbar that overlaps the first board, and a second board that is constituted by an insulating plate provided with a conductive path and overlapping the first board, at least a portion of the second board being arranged on the same level as the busbar. The plurality of terminals of the electronic component is connected to the busbar and the conductive path of the second board.

公开(公告)号：US20180252499A1

公开(公告)日：2018-09-06

申请号：US15911052

申请日：2018-03-02

Applicant: Invocon, Inc.

Inventor： Karl F. Kiefer ,  Donald Chaffee ,  Douglas Heermann ,  Brian Philpot

IPC: F41G7/00 ,  H05K1/14 ,  F41H11/02

CPC classification number: F41G7/001 ,  F41G7/224 ,  F41H11/02 ,  F41J9/08 ,  H05K1/0393 ,  H05K1/144 ,  H05K2201/041 ,  H05K2201/10151

Abstract: A time domain detection system to measure and report on hypervelocity impacts HVI between an interceptor vehicle and a target vehicle. Wherein, said time domain detection system comprises a target vehicle components installed on said target vehicle, a one or more panels arranged on a portion of said target vehicle at a potential HVI locations, and a hit detection system wired into said one or more panels. Said target vehicle components comprise at least said hit detection system, and a lines. Said one or more panels are wired into said hit detection system with said lines. Said hit detection system is configured to communicate with said one or more panels over said lines. Said one or more panels can each comprise a one or more detector panel layers, and a two or more insulator layers.

公开(公告)号：US20180242445A1

公开(公告)日：2018-08-23

申请号：US15713362

申请日：2017-09-22

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  Chengdu BOE Optoelectronics Technology Co., Ltd.

Inventor： Tingliang Liu ,  Shuo Jin ,  Yuanjie Xu

IPC: H05K1/02 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K3/36 ,  H05K3/30

CPC classification number: H05K1/0269 ,  H05K1/144 ,  H05K1/147 ,  H05K1/165 ,  H05K1/181 ,  H05K1/189 ,  H05K3/305 ,  H05K3/321 ,  H05K3/361 ,  H05K2201/041 ,  H05K2201/049 ,  H05K2201/10128 ,  H05K2203/0278 ,  H05K2203/161 ,  H05K2203/163

Abstract: The present disclosure discloses a circuit component and a method for manufacturing the same and a bonding device. The circuit component comprises a first circuit board and a second circuit board, wherein at least one of the first circuit board and the second circuit board comprises a bonding detection layer configured to be capable of detecting a bonding parameter between the first circuit board and the second circuit board; and emitting a detection signal when the bonding parameter reaches a preset value.

公开(公告)号：US10057978B2

公开(公告)日：2018-08-21

申请号：US15514864

申请日：2015-09-08

Applicant: JOLED INC.

Inventor： Shinya Ono

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  H05K1/14 ,  H05K1/11 ,  H05K3/28 ,  H05K3/00 ,  H05K3/36 ,  H01L51/52

CPC classification number: H05K1/0268 ,  G09F9/00 ,  G09F9/30 ,  G09G3/006 ,  G09G2330/12 ,  H01L51/524 ,  H05K1/118 ,  H05K1/144 ,  H05K1/189 ,  H05K3/0052 ,  H05K3/0091 ,  H05K3/28 ,  H05K3/366 ,  H05K2201/041 ,  H05K2201/10128 ,  H05K2203/162

Abstract: A display panel including: a substrate; a plurality of first connecting wires in a first portion of the substrate and connected to a first flexible printed circuit board; a plurality of second connecting wires in a second portion of the substrate and connected to a second flexible printed circuit board, the second portion being adjacent to the first portion; first and second test pads provided between the first and second portions of the substrate, the first test pad being connected to an endmost first connecting wire adjacent to the second portion, the second test pad being connected to an endmost second connecting wire adjacent to the first portion; and an electrical circuit in which the endmost first and second connecting wires are included in different power supply nodes.

公开(公告)号：US20180235088A1

公开(公告)日：2018-08-16

申请号：US15953823

申请日：2018-04-16

Applicant: Guangdong Oppo Mobile Telecommunications Corp., Ltd.

Inventor： Wenzhen Zhang

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/36 ,  H05K1/14 ,  H04M1/02 ,  H05K5/03 ,  H05K3/30 ,  H05K1/11 ,  G06F1/16 ,  G06K9/00

CPC classification number: H05K1/189 ,  G06F1/1684 ,  G06F2203/0338 ,  G06K9/00 ,  G06K9/00006 ,  H04M1/026 ,  H04M2250/12 ,  H05K1/0281 ,  H05K1/111 ,  H05K1/144 ,  H05K3/301 ,  H05K3/305 ,  H05K3/363 ,  H05K5/03 ,  H05K2201/041 ,  H05K2201/10151 ,  H05K2201/10318 ,  H05K2201/10325 ,  H05K2201/10757

Abstract: A fingerprint module includes a cover plate, a fingerprint chip, an intermediate board, and a circuit board. The cover plate defines an assembling region. The fingerprint chip is fixed in the assembling region and has a plurality of pads. The intermediate board is bonded to a surface of the fingerprint chip opposite to the cover plate to press the fingerprint chip to increase a bonding force between the fingerprint chip and the cover plate, so that there is a firm bonding between the fingerprint chip and the cover plate. The fingerprint chip is electrically connected to the intermediate board via the pads. The circuit board is electrically connected to the fingerprint chip via the intermediate board. The pads are connected to the circuit board via different wires to ensure effective transmission of electrical signals of the fingerprint chip.

公开(公告)号：US20180213640A1

公开(公告)日：2018-07-26

申请号：US15870413

申请日：2018-01-12

Applicant: KYOCERA Corporation

Inventor： Takafumi KAMEI

IPC: H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0306 ,  H05K1/0237 ,  H05K1/024 ,  H05K1/09 ,  H05K1/111 ,  H05K1/115 ,  H05K1/144 ,  H05K1/181 ,  H05K3/0014 ,  H05K3/102 ,  H05K3/1291 ,  H05K3/4629 ,  H05K3/4644 ,  H05K2201/041 ,  H05K2201/0769 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/09781

Abstract: A ceramic circuit board includes an insulating substrate composed of stacked insulating layers of an alumina-based sintered body, internal leads containing Cu embedded in the insulating substrate, and one or a plurality of metal layers containing Cu embedded in the insulating substrate, at least one of the metal layers being located nearer than the internal leads to the surface of the insulating substrate in the stacking direction, wherein at least part of the metal layer overlaps the internal leads in plan view.

公开(公告)号：US10021794B2

公开(公告)日：2018-07-10

申请号：US15346096

申请日：2016-11-08

Applicant: LG Display Co., Ltd.

Inventor： Jin-Hyun Jung ,  BuYeol Lee

IPC: H05K5/00 ,  H01L51/52 ,  H05K1/02 ,  H05K1/14 ,  G02F1/1345 ,  H05K3/36

CPC classification number: H05K5/0017 ,  G02F1/13452 ,  G02F2203/01 ,  H01L51/52 ,  H01L51/5237 ,  H05K1/0274 ,  H05K1/14 ,  H05K1/144 ,  H05K3/363 ,  H05K2201/0108 ,  H05K2201/041 ,  H05K2201/056 ,  H05K2201/10128 ,  H05K2201/10681

Abstract: Disclosed is a display device for realizing a transparent image. The display device includes a display panel, a source printed circuit board (PCB) on which a signal line is mounted, a control PCB on which a timing controller is mounted, and a circuit film connected to the display panel at one side of the circuit film and connected to the source PCB at another side. The source PCB and the control PCB are disposed to overlap each other.