公开(公告)号：US07670919B2

公开(公告)日：2010-03-02

申请号：US11323312

申请日：2005-12-30

Applicant: John J. Tang ,  Xiang Yin Zeng ,  Jiangqi He ,  Ding Hai

Inventor： John J. Tang ,  Xiang Yin Zeng ,  Jiangqi He ,  Ding Hai

IPC: H01L21/20

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48472 ,  H01L2224/49 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H05K1/111 ,  H05K1/113 ,  H05K1/162 ,  H05K3/28 ,  H05K2201/0187 ,  H05K2201/09436 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.

Abstract translation: 一种物品包括埋在焊接掩模中的顶部电极。 一种物品包括在核心结构上的顶部电极。 形成顶部电极的工艺包括减小焊接掩模厚度并在厚度较薄的焊接掩模上形成顶部电极。 形成顶部电极的工艺包括在位于芯结构的图案化部分中的高K电介质上形成顶部电极。

公开(公告)号：US07649252B2

公开(公告)日：2010-01-19

申请号：US10549986

申请日：2004-10-15

Applicant: Norio Sakai ,  Jun Harada ,  Satoshi Ishino ,  Yoshihiko Nishizawa

Inventor： Norio Sakai ,  Jun Harada ,  Satoshi Ishino ,  Yoshihiko Nishizawa

IPC: H01L23/12 ,  H01L23/06

CPC classification number: H05K1/186 ,  H01L23/5385 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4605 ,  H05K2201/0154 ,  H05K2201/09436 ,  H05K2203/1581 ,  H01L2224/0401

Abstract: A ceramic multilayer substrate has a ceramic laminate including a plurality of ceramic layers laminated, having a first main surface, and including internal circuit elements disposed in the inside, a resin layer having a bonding surface in contact with the first main surface of the ceramic laminate and a mounting surface opposite to the bonding surface, external electrodes, each disposed on the mounting surface of the resin layer and electrically connected to at least one of the internal circuit elements of the ceramic laminate, and a ground electrode, a dummy electrode, or capacitor electrodes disposed at an interface between the first main surface of the ceramic laminate and the bonding surface of the resin layer or in the inside of the resin layer.

Abstract translation: 陶瓷多层基板具有包括多个陶瓷层的陶瓷层叠体，具有第一主表面，并且包括设置在内部的内部电路元件，具有与陶瓷层叠体的第一主表面接触的接合面的树脂层 和与接合面相反的安装面，外部电极，各自设置在树脂层的安装面上，与陶瓷层叠体的至少一个内部电路元件电连接，接地电极，虚拟电极或 设置在陶瓷层叠体的第一主面与树脂层的接合面或树脂层内侧的界面处的电容电极。

公开(公告)号：US07568922B2

公开(公告)日：2009-08-04

申请号：US11304770

申请日：2005-12-16

Applicant: Takahiro Yamashita ,  Hiroyuki Watanabe ,  Kiyotaka Tsukada ,  Michio Ido ,  Morio Nakao

Inventor： Takahiro Yamashita ,  Hiroyuki Watanabe ,  Kiyotaka Tsukada ,  Michio Ido ,  Morio Nakao

IPC: H01R12/00 ,  H05K1/00

CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/3457 ,  H05K2201/0347 ,  H05K2201/09436 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/098 ,  Y10T29/49144 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: This invention provides a printed wiring board having an intensified drop impact resistance of a joint portion between pad and solder. An electrode pad comprises pad portion loaded with solder ball and a cylindrical portion projecting to the solder ball supporting the pad portion. An outer edge of the pad portion extends sideway from a cylindrical portion so that the outer edge is capable of bending. If the outer edge bends when stress is applied to the solder ball 30, stress on the outer edge of the pad portion on which stress is concentrated can be relaxed so as to intensify the joint strength between an electrode pad and solder ball.

Abstract translation: 本发明提供了一种印刷电路板，其具有焊盘和焊料之间的接合部分的强烈的耐滴落冲击性。 电极焊盘包括装载有焊球的焊盘部分和突出到支撑焊盘部分的焊球的圆柱形部分。 衬垫部分的外边缘从圆筒部分侧向延伸，使得外边缘能够弯曲。 如果当对焊球30施加应力时外边缘弯曲，则可以放松应力集中的焊盘部分的外边缘上的应力，从而加强电极焊盘和焊球之间的接合强度。

公开(公告)号：US20090174073A1

公开(公告)日：2009-07-09

申请号：US12254884

申请日：2008-10-21

Applicant: Woong Sun LEE

Inventor： Woong Sun LEE

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/247 ,  H05K3/3457 ,  H05K2201/035 ,  H05K2201/09436 ,  H01L2924/00

Abstract: A substrate for a semiconductor package includes a ball land disposed on one surface of an insulating layer. A solder resist is applied to the surface of insulating layer while leaving the ball land exposed. A coating film is applied on the exposed surface of the 1o ball land. The coating film includes a high molecular compound having metal particles. In the substrate having the ball land with the coating film formed thereon, it is not necessary to subject the substrate to a UBM formation process.

Abstract translation: 用于半导体封装的衬底包括设置在绝缘层的一个表面上的球形区域。 在绝缘层的表面上施加阻焊剂，同时露出球场。 将涂膜施加在1o球地的暴露表面上。 涂膜包括具有金属颗粒的高分子化合物。 在其上形成有涂膜的球面的基板中，不需要使基板进行UBM形成工艺。

公开(公告)号：US20090166068A1

公开(公告)日：2009-07-02

申请号：US12343784

申请日：2008-12-24

Applicant: Takeo Takahashi ,  Xiaoyu Mi ,  Tsuyoshi Yokoyama ,  Tokihiro Nishihara ,  Satoshi Ueda

Inventor： Takeo Takahashi ,  Xiaoyu Mi ,  Tsuyoshi Yokoyama ,  Tokihiro Nishihara ,  Satoshi Ueda

IPC: H05K1/00 ,  H05K1/16

CPC classification number: H05K1/16 ,  H01L2224/16 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/246 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2201/09436

Abstract: An electronic component includes: a multilayer ceramic substrate that has a penetration electrode formed therein, and has a passive element provided on the upper face thereof; an insulating film that is provided on the multilayer ceramic substrate, and has an opening above the penetration electrode; a first connecting terminal that is provided on the insulating film so as to cover the opening, and is electrically connected to the penetration electrode; and a second connecting terminal that is provided on a region of the insulating film other than the opening region.

Abstract translation: 电子部件包括：多层陶瓷基板，其具有形成在其中的穿透电极，并且在其上表面上设置无源元件; 绝缘膜，设置在所述多层陶瓷基板上，并且在所述贯通电极的上方具有开口部; 第一连接端子，设置在绝缘膜上以覆盖开口，并且电连接到穿透电极; 以及第二连接端子，其设置在除了开口区域之外的绝缘膜的区域上。

公开(公告)号：US07553750B2

公开(公告)日：2009-06-30

申请号：US11559576

申请日：2006-11-14

Applicant: Chao Wen Shih

Inventor： Chao Wen Shih

IPC: H01L21/44

CPC classification number: H05K3/243 ,  H01L21/4853 ,  H05K1/111 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0391 ,  H05K2201/09436 ,  H05K2201/0989 ,  H05K2203/054

Abstract: A method for fabricating an electrical conductive structure of a circuit board is disclosed. The method includes providing a circuit board having a plurality of first and second electrically conductive pads; forming on the circuit board an insulating protection layer having a plurality of openings for exposing the first and second electrically conductive pads; forming a metal adhesive layer on the first and second electrically conductive pads; forming a conductive layer on the insulating protection layer and on the metal adhesive layer formed on the first and second electrically conductive pads, the conductive layer being electrical conductive to the first and second electrically conductive pads; forming on the conductive layer a resist layer having a plurality of openings for exposing the conductive layer on the second electrically conductive pads; and electroplating a conductive structure on the conductive layer on the second electrically conductive pads exposed from the openings.

Abstract translation: 公开了一种用于制造电路板的导电结构的方法。 该方法包括提供具有多个第一和第二导电焊盘的电路板; 在所述电路板上形成具有用于暴露所述第一和第二导电焊盘的多个开口的绝缘保护层; 在第一和第二导电焊盘上形成金属粘合剂层; 在绝缘保护层和形成在第一和第二导电焊盘上的金属粘合剂层上形成导电层，导电层与第一和第二导电焊盘导电; 在所述导电层上形成具有多个开口的抗蚀剂层，用于将所述导电层暴露在所述第二导电焊盘上; 以及在从所述开口暴露的所述第二导电焊盘上的所述导电层上电镀导电结构。

公开(公告)号：US20090101398A1

公开(公告)日：2009-04-23

申请号：US12227364

申请日：2007-05-15

Applicant: Hannes Voraberger ,  Gerhard Schmid ,  Markus Riester ,  Johannes Stahr

Inventor： Hannes Voraberger ,  Gerhard Schmid ,  Markus Riester ,  Johannes Stahr

IPC: H05K3/30 ,  H05K1/00

CPC classification number: H01L23/498 ,  H01L21/4846 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/186 ,  H05K3/005 ,  H05K3/107 ,  H05K3/4644 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/09436 ,  H05K2201/10734 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a method for fixing an electronic component (3) on a printed circuit board (2), and contact-connecting the electronic component (3) to the printed circuit board (2), the following steps are provided: —providing the printed circuit board (2) having a plurality of contact and connection pads (8), —providing the electronic component (3) having a number of contact and connection locations (5) corresponding to the plurality of contact and connection pads (8) of the printed circuit board (2), with a mutual spacing reduced in comparison with the spacing of the contact and connection pads (8) of the printed circuit board (2), and —arranging or forming at least one interlayer (4) for routing the contact and connection locations (5) of the electronic component (3) between the contact and connection pads (8) of the printed circuit board (2) and the contact and connection locations (5) of the electronic component (3). A method for producing an interlayer (4) for routing and a system having a printed circuit board (2) and an electronic component (3) using the interlayer (4) for routing are also provided.

Abstract translation: 在将电子部件（3）固定在印刷电路板（2）上并且将电子部件（3）与印刷电路板（2）接触的方法中，提供以下步骤：提供印刷电路 具有多个接触和连接焊盘（8）的板（2）， - 提供具有对应于印刷的多个接触和连接焊盘（8）的多个接触和连接位置（5）的电子部件（3） 电路板（2），与印刷电路板（2）的接触和连接焊盘（8）的间隔相比相互间隔减小，并且 - 安排或形成至少一个中间层（4），用于布线接触 以及电子部件（3）的连接位置（5）与印刷电路板（2）的接触焊盘（8）和电子部件（3）的触点和连接位置（5）之间。 还提供了一种制造用于布线的中间层（4）的方法和具有使用中间层（4）进行布线的印刷电路板（2）和电子部件（3）的系统。

公开(公告)号：US20090095519A1

公开(公告)日：2009-04-16

申请号：US11872870

申请日：2007-10-16

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: H05K1/00 ,  H05K3/42

CPC classification number: H01L24/10 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/112 ,  H05K2201/0769 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/0979 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49179 ,  H01L2924/00

Abstract: An electrical structure and method of forming. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.

Abstract translation: 一种电气结构和成型方法。 电结构包括互连结构和衬底。 衬底包括导电焊盘和电连接到导电焊盘的多个导线迹线。 导电焊盘电连接和机械连接到互连结构。 多条导线包括第一线迹线，第二线迹线，第三线迹线和第四线迹线。 第一线迹和第二线迹均电连接到导电垫的第一侧。 第三线迹电连接到导电垫的第二侧。 第四线迹电连接到所述第一导电焊盘的第三侧。 多个导线配置成分布电流。

公开(公告)号：US20090020323A1

公开(公告)日：2009-01-22

申请号：US12218891

申请日：2008-07-18

Applicant: Chien-Te Chen ,  Ke-Chuan Yang ,  Hung-Ming Chang

Inventor： Chien-Te Chen ,  Ke-Chuan Yang ,  Hung-Ming Chang

IPC: H05K1/09 ,  H05K3/10

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/114 ,  H05K3/108 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/09436 ,  H05K2203/025 ,  H05K2203/0733 ,  Y10T29/49149 ,  H01L2924/00

Abstract: A circuit board structure and a method for fabricating the same are disclosed, including providing a core board having conductive traces and solder pads respectively formed thereon, wherein width of the solder pads corresponds to that of the conductive traces, and pitch between adjacent solder pads is made wide enough to allow multiple conductive traces to pass through; forming on the core board an insulating layer with openings for exposing the solder pads therefrom; forming on the insulating layer a plurality of extending pads electrically connected to the solder pads respectively, wherein the projection area of the extending pads is larger than that of the corresponding solder pads and covers conductive traces adjacent to the corresponding solder pads. Thus, more conductive traces are allowed to pass between adjacent solder pads and meanwhile, the extending pads provide an effective solder ball wetting area for achieving good solder joints and sufficient height after collapse.

Abstract translation: 公开了一种电路板结构及其制造方法，包括提供具有分别形成在其上的导电迹线和焊盘的芯板，其中焊盘的宽度对应于导电迹线的宽度，相邻焊盘之间的间距是 足够宽以允许多个导电迹线通过; 在所述芯板上形成具有用于从其露出焊盘的开口的绝缘层; 在所述绝缘层上形成分别电连接到所述焊盘的多个延伸焊盘，其中所述延伸焊盘的所述投影区域大于相应焊接焊盘的所述投影区域并且覆盖与相应焊盘相邻的导电迹线。 因此，允许更多的导电迹线在相邻焊盘之间通过，同时，延伸焊盘提供有效的焊球润湿区域，以实现良好的焊点和崩溃后的足够的高度。

公开(公告)号：US20080265411A1

公开(公告)日：2008-10-30

申请号：US11979980

申请日：2007-11-13

Applicant: Wen-Hung Hu

Inventor： Wen-Hung Hu

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H05K3/3452 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2924/00014 ,  H05K1/112 ,  H05K2201/09236 ,  H05K2201/09436 ,  H05K2201/09854 ,  H05K2203/054 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A structure of a packaging substrate and a method for making the same are disclosed, wherein the structure comprises: a substrate body having a circuit layer on the surface thereof, wherein the circuit layer has a plurality of conductive pads which are each formed in a flat long shape to enhance the elasticity of circuit layout; a solder mask disposed on the substrate body and having a plurality of openings corresponding to and exposing the conductive pads, wherein the openings are each formed in a flat long shape; and a metal bump disposed in each of the openings of the solder mask and on each of the corresponding conductive pads.

Abstract translation: 公开了一种封装基板的结构及其制造方法，其特征在于，所述结构体包括：表面具有电路层的基板主体，其中，所述电路层具有多个导电焊盘， 长形增强电路布局的弹性; 焊接掩模，其设置在所述基板主体上并且具有对应于并暴露所述导电焊盘的多个开口，其中所述开口各自形成为平坦的长形状; 以及设置在焊料掩模的每个开口中和每个相应导电焊盘上的金属凸块。