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    Method of making high speed interposer
    91.
    发明申请
    Method of making high speed interposer 审中-公开
    制作高速内插器的方法

    公开(公告)号：US20080120835A1

    公开(公告)日：2008-05-29

    申请号：US12010469

    申请日：2008-01-25

    Applicant: David V. Caletka ,  Frank D. Egitto

    Inventor： David V. Caletka ,  Frank D. Egitto

    IPC: H05K3/42 ,  H05K3/10

    CPC classification number: H05K1/0219 ,  H01R12/523 ,  H01R13/2414 ,  H05K1/113 ,  H05K3/4046 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/0959 ,  H05K2201/09809 ,  H05K2201/10303 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A method of making a high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.

    Abstract translation: 一种制造高速插入器的方法，其包括具有交替取向的介电层和导电层的基板，其形成基板，从基板的一个相对表面延伸到第二相对表面的开口，位于开口内的导电构件也从 以及在高频信号通过导电构件的过程中基本上围绕导电构件定位的多个屏蔽构件，从而提供屏蔽。

    METHOD FOR FABRICATING CLOSED VIAS IN A PRINTED CIRCUIT BOARD
    92.
    发明申请
    METHOD FOR FABRICATING CLOSED VIAS IN A PRINTED CIRCUIT BOARD 失效
    在印刷电路板上制作封闭VIAS的方法

    公开(公告)号：US20080119041A1

    公开(公告)日：2008-05-22

    申请号：US11557690

    申请日：2006-11-08

    Applicant: Jaroslaw A. Magera ,  Gregory J. Dunn ,  Kathy D. Leganski

    Inventor： Jaroslaw A. Magera ,  Gregory J. Dunn ,  Kathy D. Leganski

    IPC: H05K3/30 ,  H01L21/4763

    CPC classification number: H05K3/427 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/097 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49165

    Abstract: A method for forming closed vias in a multilayer printed circuit board. A dielectric layer is laminated to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture faces the other dielectric layer. Resin from one dielectric layer fills the cavities of approximately one half of the closed vias, and resin from the other dielectric layer fills the circular cavities of the remainder of the closed vias. The total amount of resin migrated from each of the dielectric layers into the closed via cavities is approximately equal.

    Abstract translation: 一种在多层印刷电路板中形成封闭通孔的方法。 电介质层被层叠在每侧具有金属层的中心芯的一侧。 第二电介质层被层压到中心芯的另一侧。 已经通过部分地穿过但不完全穿透中心芯而形成中心芯上的闭合的通孔，然后通过直径小得多的孔从相对侧完成通孔，以形成完全穿透中心芯的通路 从一边到另一边。 然后通孔用金属电镀以基本上闭合较小的孔。 闭合通孔的大约一半被定位成使得闭合孔面对一个电介质层，并且其余的封闭通孔被定位成使得闭合孔面对另一介电层。 来自一个介电层的树脂填充了大约一半的封闭通孔的空腔，而另一个介电层的树脂填充了其余的封闭通孔的圆形空腔。 从每个介电层迁移到封闭通孔中的树脂的总量近似相等。

    MULTI-LAYER PRINTED WIRING BOARD AND MANUFACTURING METHOD THEREOF
    93.
    发明申请
    MULTI-LAYER PRINTED WIRING BOARD AND MANUFACTURING METHOD THEREOF 有权
    多层印刷接线板及其制造方法

    公开(公告)号：US20080060840A1

    公开(公告)日：2008-03-13

    申请号：US11832892

    申请日：2007-08-02

    Applicant: Youhong WU

    Inventor： Youhong WU

    IPC: H01R12/06 ,  H05K3/46

    CPC classification number: H05K1/115 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  Y10T29/49165

    Abstract: A multi-layer printed wiring board has a core substrate, a throughhole structure, a first interlayer insulation layer, a first via, a second interlayer insulation layer and a second via. The core substrate has a throughhole opening, and the throughhole structure is formed in the throughhole opening. The first interlayer insulation layer is formed over the core substrate. The first via is formed in the first interlayer insulation layer and has a bottom portion having a first radius. The second interlayer insulation layer is formed over the first interlayer insulation layer and the first via. The second via is formed in the second interlayer insulation layer and has a bottom portion having a second radius greater than the first radius. The first via is positioned inside a circle having a radius (D1) from a gravity center of the throughhole opening, and the radius (D1) of the circle satisfies a formula, (D1)=(R)+(r)/3, where (R) represents a radius of the throughhole opening and (r) represents the first radius of the first via.

    Abstract translation: 多层印刷电路板具有核心基板，通孔结构，第一层间绝缘层，第一通孔，第二层间绝缘层和第二通孔。 核心基板具有通孔开口，并且通孔结构形成在通孔开口中。 在芯基板上形成第一层间绝缘层。 第一通孔形成在第一层间绝缘层中，并且具有第一半径的底部。 第二层间绝缘层形成在第一层间绝缘层和第一通孔之上。 第二通孔形成在第二层间绝缘层中，并且具有大于第一半径的第二半径的底部。 第一通孔位于从通孔开口重心的半径（D1）的圆内，圆的半径（D1）满足式（D1）=（R）+（r）/ 3， 其中（R）表示通孔开口的半径，（r）表示第一通孔的第一半径。

    Structure for memory cards
    94.
    发明授权
    Structure for memory cards 有权
    存储卡结构

    公开(公告)号：US07335034B1

    公开(公告)日：2008-02-26

    申请号：US11621566

    申请日：2007-01-10

    Applicant: Chin-Tong Liu

    Inventor： Chin-Tong Liu

    IPC: H01R12/00

    CPC classification number: G06K19/077 ,  G06K19/07732 ,  H05K1/117 ,  H05K3/284 ,  H05K2201/09063 ,  H05K2201/0959

    Abstract: A structure for memory card is provided, including a bottom shell, a circuit substrate, a top shell, and a covering layer. The bottom shell includes a base seat of a smaller area size. The circuit substrate includes a first surface and an opposite second surface. The first surface includes chips and circuits, and the second surface includes an electrical contact part. The chips and the circuits are connected to the electrical contact part. The circuit substrate also includes a plurality of connecting holes. The connecting holes are preferably located around the electrical contact part. The circuit substrate is attached to the base seat of the bottom shell on the first surface, and the top shell covers the second surface of the circuit substrate, with the electrical contact part exposed. The covering layer is formed directly on the circumference and the seam of the top shell, bottom shell, and circuit substrate, and fills the connecting holes to engage the top shell and the bottom shell. The covering layer forms the memory card of a standard physical specification.

    Abstract translation: 提供了一种用于存储卡的结构，包括底壳，电路基板，顶壳和覆盖层。 底壳包括较小面积尺寸的基座。 电路基板包括第一表面和相对的第二表面。 第一表面包括芯片和电路，第二表面包括电接触部分。 芯片和电路连接到电接触部分。 电路基板还包括多个连接孔。 连接孔优选地位于电接触部分周围。 电路基板被附接到第一表面上的底壳的基座，并且顶壳覆盖电路基板的第二表面，电接触部分露出。 覆盖层直接形成在顶壳，底壳和电路基板的圆周和接缝上，并填充连接孔以接合顶壳和底壳。 覆盖层形成标准物理规格的存储卡。

    High speed interposer
    96.
    发明申请
    High speed interposer 有权
    高速插入器

    公开(公告)号：US20070289773A1

    公开(公告)日：2007-12-20

    申请号：US11454896

    申请日：2006-06-19

    Applicant: David V. Caletka ,  Frank D. Egitto

    Inventor： David V. Caletka ,  Frank D. Egitto

    IPC: H05K1/11 ,  H01R12/04

    CPC classification number: H05K1/0219 ,  H01R12/523 ,  H01R13/2414 ,  H05K1/113 ,  H05K3/4046 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/0959 ,  H05K2201/09809 ,  H05K2201/10303 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.

    Abstract translation: 高速插入器，其包括具有交替取向的介电层和导电层的基板，其形成基板，从基板的一个相对表面延伸到第二相对表面的开口，定位在开口内并且还从表面延伸到表面的导电构件 并且在一些实施例中超越）以及基本上围绕导电构件定位的多个屏蔽构件，从而在高频信号通过导电构件期间提供屏蔽。

    Method of manufacturing build-up printed circuit board
    98.
    发明申请
    Method of manufacturing build-up printed circuit board 失效
    制造印刷电路板的方法

    公开(公告)号：US20070261234A1

    公开(公告)日：2007-11-15

    申请号：US11709215

    申请日：2007-02-22

    Applicant: Jong Seok Song ,  Taehoon Kim ,  Dong Sun Kim ,  Hye Yeon Cha

    Inventor： Jong Seok Song ,  Taehoon Kim ,  Dong Sun Kim ,  Hye Yeon Cha

    IPC: H01K3/10 ,  H05K3/10 ,  H05K3/02

    CPC classification number: H05K3/381 ,  H05K3/108 ,  H05K3/146 ,  H05K3/4069 ,  H05K3/426 ,  H05K3/4602 ,  H05K2201/0959 ,  H05K2203/092 ,  H05K2203/1152 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: Disclosed is a method of manufacturing a build-up printed circuit board, in which the circuit of a build-up printed circuit board including a core layer and an outer layer is realized by forming the metal seed layer of the core layer using a dry process, consisting of ion beam surface treatment and vacuum deposition, instead of a conventional wet process, including a wet surface roughening process and electroless plating. When the wet process is replaced with the dry process in the method of the invention, the circuit layer can be formed in an environmentally friendly manner, and as well, all circuit layers of the substrate including the core layer and the outer layer can be manufactured through a semi-additive process. Further, the peel strength between the resin substrate and the metal layer can be increased, thus realizing a highly reliable fine circuit.

    Abstract translation: 公开了一种积层印刷电路板的制造方法，其中通过使用干法形成芯层的金属种子层来实现包括芯层和外层的积层印刷电路板的电路 ，由离子束表面处理和真空沉积组成，代替常规的湿法，包括湿表面粗糙化处理和无电镀。 当在本发明的方法中用干法代替湿法时，电路层可以以环境友好的方式形成，并且可以制造包括芯层和外层的基片的所有电路层 通过半加成过程。 此外，可以提高树脂基板和金属层之间的剥离强度，从而实现高可靠性的精细电路。

    Shielded through-via
    99.
    发明申请
    Shielded through-via 有权
    屏蔽通孔

    公开(公告)号：US20070222021A1

    公开(公告)日：2007-09-27

    申请号：US11373223

    申请日：2006-03-10

    Applicant: Jun Yao

    Inventor： Jun Yao

    IPC: H01L29/00

    CPC classification number: H01L23/48 ,  H01L23/481 ,  H01L23/552 ,  H01L2223/6622 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0222 ,  H05K1/0239 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09809 ,  H01L2924/00

    Abstract: A shielded through-via that reduces the effect of parasitic capacitance between the through-via and surrounding wafer while providing high isolation from neighboring signals. A shield electrode is formed in the insulating region and spaced apart from the through-via. A coupling element couples at least the time-varying portion of the signal carried on the through-via to the shield electrode. This reduces the effect of any parasitic capacitance between the through-via and the shield electrode, hence the surrounding wafer.

    Abstract translation: 一种屏蔽通孔，可减少通孔和周围晶片之间的寄生电容的影响，同时提供与相邻信号的高隔离度。 屏蔽电极形成在绝缘区域中并且与通孔间隔开。 耦合元件至少将通孔上承载的信号的时变部分耦合到屏蔽电极。 这减少了通孔和屏蔽电极之间的任何寄生电容的影响，从而降低了周围的晶片。

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