公开(公告)号：US20100236819A1

公开(公告)日：2010-09-23

申请号：US12724200

申请日：2010-03-15

Applicant: Wen-Chung Chiang ,  Keng-Chung Wu ,  Ying-Chi Hsieh ,  Cheng-Kang Lu ,  Ming-Huang Fu

Inventor： Wen-Chung Chiang ,  Keng-Chung Wu ,  Ying-Chi Hsieh ,  Cheng-Kang Lu ,  Ming-Huang Fu

IPC: H05K1/09 ,  B05D5/12 ,  B32B38/10 ,  H05K1/03 ,  H05K1/11 ,  G03F7/20

CPC classification number: H05K3/0029 ,  H05K1/0306 ,  H05K3/4061 ,  H05K2201/0355 ,  H05K2201/0969 ,  H05K2203/0554

Abstract: A method for making a printed circuit board includes: (a) preparing a laminate having a ceramic substrate, first and second metal foils disposed on two opposite surfaces of the ceramic substrate, and a through hole extending through the ceramic substrate and the first and second metal foils; (b) filling the through hole with a metal paste such that the metal paste is in contact with the first and second metal foils; and (c) sintering the metal paste and the laminate such that the metal paste is connected electrically to the first and second metal foils. A printed circuit board made according to the method is also disclosed.

Abstract translation: 制造印刷电路板的方法包括：（a）制备具有陶瓷基板的层压体，设置在陶瓷基板的两个相对表面上的第一和第二金属箔，以及延伸穿过陶瓷基板的通孔和第一和第二 金属箔 （b）用金属膏填充通孔，使得金属膏与第一和第二金属箔接触; 和（c）将金属糊和层压体烧结，使得金属膏与第一和第二金属箔电连接。 还公开了根据该方法制造的印刷电路板。

公开(公告)号：US20100214752A1

公开(公告)日：2010-08-26

申请号：US12543644

申请日：2009-08-19

Applicant: Keisuke Shimizu ,  Yoichiro Kawamura

Inventor： Keisuke Shimizu ,  Yoichiro Kawamura

IPC: H05K1/18 ,  H05K3/32

CPC classification number: H05K1/188 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24227 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K3/025 ,  H05K3/4697 ,  H05K2201/0969 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  Y10T29/49139 ,  H01L2924/00

Abstract: A wiring board has a substrate, a conductive pattern formed over the substrate, and an electronic component mounted to the substrate and having an electrode. The electrode of the electronic component is connected to the conductive pattern through a via hole. The thickness of the electrode of the electronic component is made less than the thickness of the conductive pattern.

Abstract translation: 布线板具有衬底，形成在衬底上的导电图案，以及安装到衬底并具有电极的电子部件。 电子部件的电极通过通孔与导电图案连接。 使电子部件的电极的厚度小于导电图案的厚度。

公开(公告)号：US20100181207A1

公开(公告)日：2010-07-22

申请号：US12356083

申请日：2009-01-20

Applicant: Sung-Ling Su

Inventor： Sung-Ling Su

IPC: H01B13/00 ,  C25F3/02

CPC classification number: H05K1/167 ,  C25D5/022 ,  C25D7/12 ,  H05K3/062 ,  H05K3/064 ,  H05K3/184 ,  H05K2201/0969 ,  H05K2203/1453 ,  Y10T29/49082 ,  Y10T29/49099 ,  Y10T29/49124 ,  Y10T29/49151

Abstract: A method for fabricating the embedded thin film resistors of a printed circuit board is provided. The embedded thin film resistors are formed using a resistor layer built in the printed circuit board. In comparison with conventional discrete resistors, embedded thin film resistors contribute to a smaller printed circuit board as the space for installing conventional resistors is saved, and better signal transmission speed and quality as the parasitic capacitive reactance effect caused by two contact ends of the conventional resistors is also avoided. The method for fabricating the embedded thin film resistors provided by the invention can be conducted using the process and equipment for conventional printed circuit boards and thereby saving the investment on new types of equipment. The method can be applied in the mass production of printed circuit boards and thereby reduce the manufacturing cost significantly.

Abstract translation: 提供一种制造印刷电路板的嵌入式薄膜电阻器的方法。 嵌入式薄膜电阻器使用内置在印刷电路板中的电阻层形成。 与传统的分立电阻器相比，嵌入式薄膜电阻器有助于更小的印刷电路板，因为节省了安装常规电阻器的空间，并且由于传统电阻器的两个接触端引起的寄生电容电抗效应，信号传输速度和质量更好 也避免了。 本发明提供的嵌入式薄膜电阻器的制造方法可以使用常规印刷电路板的工艺和设备进行，从而节省对新型设备的投资。 该方法可以用于批量生产印刷电路板，从而显着降低制造成本。

公开(公告)号：US20100180437A1

公开(公告)日：2010-07-22

申请号：US12603071

申请日：2009-10-21

Applicant: William E. McKinzie, III

Inventor： William E. McKinzie, III

IPC: H01R43/00

CPC classification number: H01P1/20 ,  H01P1/2005 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0236 ,  H05K1/0239 ,  H05K1/162 ,  H05K1/165 ,  H05K1/181 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09609 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A hybrid electromagnetic bandgap (EBG) structure for broadband suppression of noise on printed wiring boards includes an array of coplanar patches interconnected into a grid by series inductances, and a corresponding array of shunt LC networks connecting the coplanar patches to a second conductive plane. This combination of series inductances and shunt resonant vias lowers the cutoff frequency for the fundamental stopband. The series inductances and shunt capacitances may be implemented using surface mount component technology, or printed traces. Patches may also be interconnected by coplanar coupled transmission lines. The even and odd mode impedances of the coupled lines may be increased by forming slots in the second conductive plane disposed opposite to the transmission line, lowering the cutoff frequency and increasing the bandwidth of the fundamental stopband. Coplanar EBG structures may be integrated into power distribution networks of printed wiring boards for broadband suppression of electromagnetic noise.

Abstract translation: 用于宽带抑制印刷电路板上的噪声的混合电磁带隙（EBG）结构包括通过串联电感互连到电网中的共面贴片阵列，以及将共面贴片连接到第二导电平面的相应阵列的分流LC网络。 串联电感和并联谐振通孔的组合降低了基波阻带的截止频率。 串联电感和分流电容可以使用表面贴装元件技术或印刷迹线实现。 补片也可以通过共面耦合传输线相互连接。 可以通过在与传输线相对布置的第二导电平面中形成槽，降低截止频率并增加基带阻带的带宽来增加耦合线的偶模和奇模阻抗。 共面EBG结构可以集成到用于宽带抑制电磁噪声的印刷线路板的配电网络中。

公开(公告)号：US07755449B2

公开(公告)日：2010-07-13

申请号：US12217315

申请日：2008-07-03

Applicant: Ki-Jae Song

Inventor： Ki-Jae Song

IPC: H01P3/08 ,  H03H7/38

CPC classification number: H05K1/0224 ,  H01P3/085 ,  H01P5/12 ,  H05K1/0253 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09254 ,  H05K2201/0969

Abstract: A printed circuit board (PCB) including an impedance-matched strip transmission line includes a strip transmission line including a main line and at least one pair of branch lines branching off from the main line. An upper ground layer is disposed over the strip transmission line and has upper opening parts corresponding in position to the branch lines. A lower ground layer is disposed under the strip transmission line and has lower opening parts corresponding in position to the branch lines. The upper and lower opening parts are symmetric about the branch lines of the strip transmission line.

Abstract translation: 包括阻抗匹配条形传输线的印刷电路板（PCB）包括带状传输线，其包括主线和从主线分支的至少一对分支线。 上部接地层设置在带状传输线上方，并具有与分支线对应的上部开口部分。 较低的接地层设置在带状传输线下方，并且具有对应于分支线位置的较低开口部分。 上开口部分和下开口部分关于条带传输线的分支线是对称的。

公开(公告)号：US20100142115A1

公开(公告)日：2010-06-10

申请号：US12499762

申请日：2009-07-08

Applicant: Hyun-Cheol Bae ,  Kwang-Seong Choi ,  Ju Yeon Hong ,  Jong Tae Moon ,  Yong il Jun

Inventor： Hyun-Cheol Bae ,  Kwang-Seong Choi ,  Ju Yeon Hong ,  Jong Tae Moon ,  Yong il Jun

IPC: H01G5/00 ,  H01G7/00 ,  B32B38/04

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01G4/38 ,  H01G4/40 ,  H05K1/0206 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/4629 ,  H05K2201/0187 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2203/171 ,  Y10T29/43 ,  Y10T156/1056

Abstract: Provided are a buried capacitor, a method of manufacturing the same, and a method of changing a capacitance thereof. The buried capacitor includes an upper electrode including at least one first hole, a lower electrode including at least one second hole, and a dielectric interposed between the upper electrode and the lower electrode.

Abstract translation: 提供一种埋电容器，其制造方法和改变其电容的方法。 掩埋电容器包括上电极，其包括至少一个第一孔，包括至少一个第二孔的下电极和介于上电极和下电极之间的电介质。

公开(公告)号：US07719650B2

公开(公告)日：2010-05-18

申请号：US11481974

申请日：2006-07-07

Applicant: Saori Sugiyama ,  Yasuko Gotoh

Inventor： Saori Sugiyama ,  Yasuko Gotoh

IPC: G02F1/1343

CPC classification number: G02F1/1345 ,  H05K1/0306 ,  H05K1/117 ,  H05K3/244 ,  H05K3/361 ,  H05K2201/0326 ,  H05K2201/0969 ,  Y10T29/49121

Abstract: The proceeding of peeling of a conductive layer in the vicinity of terminals is prevented. A display panel includes a conductive layer extending to the outside of terminals, and the conductive layer has slits extending in directions from one end face to the other end face alternately at two end faces along the extending direction of the conductive layer.

Abstract translation: 阻止在端子附近剥离导电层的过程。 显示面板包括延伸到端子外部的导电层，并且导电层具有在沿着导电层的延伸方向的两个端面处交替地从一个端面到另一个端面的方向上延伸的狭缝。

公开(公告)号：US07658622B2

公开(公告)日：2010-02-09

申请号：US12386592

申请日：2009-04-21

Applicant: Victor L. Bartholomew

Inventor： Victor L. Bartholomew

IPC: H01R12/00

CPC classification number: H05K1/0219 ,  H05K1/0201 ,  H05K1/0293 ,  H05K1/117 ,  H05K3/3405 ,  H05K3/3452 ,  H05K2201/0305 ,  H05K2201/062 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09354 ,  H05K2201/0969 ,  H05K2201/10356 ,  H05K2203/173 ,  Y10S439/943 ,  Y10T29/49155

Abstract: A transition circuit board for transitioning a cable to a connector is provided. A circuit board has an outer surface with a circuit trace, ground plane and ground link provided thereon. A cable pad and a contact pad are provided at opposite ends of the circuit trace. The ground link is electrically common with the ground plane and is located adjacent to, and separated by a space from, the circuit trace. An insulating coating is provided over at least part of the circuit trace, the ground plane and the outer surface of the circuit board. The insulating coating has a mask aperture there-through exposing an uncoated portion of the circuit trace and the ground link. A conductive jumper material is provided on the uncoated portion of the circuit trace and the ground link to electrically join the circuit trace with the ground plane.

Abstract translation: 提供了一种用于将电缆转换到连接器的转换电路板。 电路板具有外表面，其上设置有电路迹线，接地平面和接地链路。 在电路迹线的相对端设有电缆垫和接触垫。 接地链路与接地平面电气相同，并且位于与电路迹线相邻并且与电路迹线隔开的空间中。 在电路板的至少一部分，接地平面和电路板的外表面上提供绝缘涂层。 绝缘涂层在其上具有掩模孔，通过暴露电路迹线的未涂覆部分和接地链路。 在电路迹线的未涂覆部分和接地链路上提供导电跳线材料，以将电路迹线与接地平面电连接。

公开(公告)号：US07656644B2

公开(公告)日：2010-02-02

申请号：US11972579

申请日：2008-01-10

Applicant: Cengiz A. Palanduz ,  Dustin P. Wood

Inventor： Cengiz A. Palanduz ,  Dustin P. Wood

IPC: H01G4/228

CPC classification number: H05K1/162 ,  H01G4/1209 ,  H01G4/20 ,  H01G4/33 ,  H01L2224/16225 ,  H05K1/0306 ,  H05K1/097 ,  H05K3/4629 ,  H05K3/4641 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/10015 ,  H05K2201/10545 ,  Y10T29/435

Abstract: A method including depositing a suspension of a colloid having an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device having a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate having at least one capacitor structure formed on a surface, the capacitor structure having a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material has columnar grains.

Abstract translation: 一种方法，包括在衬底上沉积具有一定量的陶瓷材料的纳米颗粒的胶体的悬浮液; 并对悬浮液进行热处理以形成薄膜。 一种方法，包括将陶瓷材料的多个纳米颗粒沉积在衬底的表面上的预定位置; 并对多个纳米颗粒进行热处理以形成薄膜。 一种包括具有微处理器的计算设备的系统，所述微处理器通过衬底耦合到印刷电路板，所述衬底具有形成在表面上的至少一个电容器结构，所述电容器结构具有第一电极，第二电极和陶瓷 设置在第一电极和第二电极之间的材料，其中陶瓷材料具有柱状晶粒。

公开(公告)号：US07655870B2

公开(公告)日：2010-02-02

申请号：US11829972

申请日：2007-07-30

Applicant: Liang-Yao Chang ,  Shou-Kuo Hsu

Inventor： Liang-Yao Chang ,  Shou-Kuo Hsu

IPC: H05K1/03

CPC classification number: H05K1/0225 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09972

Abstract: An exemplary printed circuit board includes a power plane, and a ground plane. The power plane includes two power modules, and an insulating medium for insulating the two power modules from each other. The ground plane is insulated from the power plane, a plurality of slots is defined in the ground plane and located close to facing edges of the two power modules, and the slots are arranged in rows along the facing edges of the two power modules.

Abstract translation: 示例性印刷电路板包括电源平面和接地平面。 电力平面包括两个电源模块和用于将两个电源模块彼此绝缘的绝缘介质。 接地层与电源平面绝缘，多个槽位于接地平面内，靠近两个电源模块的相对边缘，并沿着两个电源模块的相对边缘排成行。