公开(公告)号：US20080317402A1

公开(公告)日：2008-12-25

申请号：US12118344

申请日：2008-05-09

Applicant: Hiroaki KODAMA ,  Kazuhito Yamada

Inventor： Hiroaki KODAMA ,  Kazuhito Yamada

IPC: G02B6/13 ,  H05K3/00

CPC classification number: G02B6/12002 ,  G02B6/43 ,  H05K1/0274 ,  H05K3/005 ,  H05K3/107 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2203/0108

Abstract: The optical/electrical composite wiring board comprises a lower insulating layer that also serves as a lower clad; a upper insulating layer that also serves as an upper clad; a core that is placed between the lower insulating layer and the upper insulating layer and has a predetermined optical wiring pattern; and a conductor layer that is placed along with the core between the lower insulating layer and the upper insulating layer and has a predetermined electrical wiring pattern. Herein, the core and the conductor layer are formed via a short manufacturing method, whereby the concave portion for optical wiring and the concave portion for electrical wiring are formed on the lower insulating layer by press process, and a core material and conductor material are filled into each of the concave portions, and afterward, the core material and conductor material are ground until they are flush with the upper surface of the lower insulating layer.

Abstract translation: 光电复合布线板包括也用作下包层的下绝缘层; 也用作上部包层的上部绝缘层; 放置在下绝缘层和上绝缘层之间并具有预定光布线图案的芯; 以及导体层，其与所述芯在所述下绝缘层和所述上绝缘层之间放置并且具有预定的电布线图案。 这里，通过短的制造方法形成芯和导体层，由此通过冲压加工在下绝缘层上形成用于光布线的凹部和电布线用凹部，并且填充芯材和导体材料 在每个凹部中分离，然后将芯材和导体材料研磨成与下绝缘层的上表面齐平。

公开(公告)号：US20080283288A1

公开(公告)日：2008-11-20

申请号：US12219381

申请日：2008-07-21

Applicant: Jee-Soo Mok ,  Chang-Sup Ryu ,  Eung-Suek Lee ,  Youn-Soo Seo ,  Hee-Bum Shin ,  Yoong Oh ,  Byung-Bae Seo ,  Tae-Kyoung Kim ,  Dong-Jin Park

Inventor： Jee-Soo Mok ,  Chang-Sup Ryu ,  Eung-Suek Lee ,  Youn-Soo Seo ,  Hee-Bum Shin ,  Yoong Oh ,  Byung-Bae Seo ,  Tae-Kyoung Kim ,  Dong-Jin Park

IPC: H05K1/11

CPC classification number: H05K3/462 ,  H01R12/523 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0353 ,  Y10T29/49155

Abstract: A printed circuit board using paste bumps and manufacturing method thereof are disclosed. The method of manufacturing a printed circuit board using paste bumps, includes: (a) perforating a core board to form at least one via hole, (b) filling the at least one via hole by fill-plating and forming a circuit pattern on at least one surface of the core board, (c) stacking a paste bump board on at least one surface of the core board, and (d) forming an outer layer circuit on a surface of the paste bump board, a structurally stable all-layer IVH structure can be implemented due to increased strength in the BVH's of the plated core boards, the manufacture time can be reduced due to parallel processes and collective stacking, implementing micro circuits can be made easy due to the copper foils of the paste bump boards stacked on the outermost layers, the manufacture costs can be reduced as certain plating and drilling processes may be omitted, the interlayer connection area is increased between circuit patterns for improved connection reliability, and dimple coverage can be obtained.

Abstract translation: 公开了一种使用糊状凸块的印刷电路板及其制造方法。 使用糊状凸块制造印刷电路板的方法包括：（a）穿孔芯板以形成至少一个通孔，（b）通过填充电镀填充至少一个通孔并在其上形成电路图案 芯板的至少一个表面，（c）在芯板的至少一个表面上堆叠焊料凸块，以及（d）在焊料凸块的表面上形成外层电路，结构稳定的全层 由于镀层芯板的BVH的强度增加，可以实现IVH结构，由于并行处理和集体堆叠，制造时间可以减少，由于糊状凸块的铜箔堆叠而实现微电路变得容易 在最外层，可以减少制造成本，因为可以省略某些电镀和钻孔工艺，在电路图案之间增加层间连接面积以提高连接可靠性，并且可以获得凹坑覆盖 d。

公开(公告)号：US07453704B2

公开(公告)日：2008-11-18

申请号：US11404771

申请日：2006-04-17

Applicant: Makoto Tanaka ,  Yuichi Koga

Inventor： Makoto Tanaka ,  Yuichi Koga

IPC: H05K7/00

CPC classification number: G06F1/1616 ,  G06F1/1656 ,  G06F1/18 ,  H01L2224/16225 ,  H01L2924/10158 ,  H01L2924/15311 ,  H05K1/114 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2203/1572 ,  Y02P70/611

Abstract: According to one embodiment, a printed wiring board includes, a main body including an obverse side with an obverse wiring layer, and a reverse side with a reverse wiring layer first pads provided on the obverse side in a first region defined thereon, and to be connected to terminals arranged on a surface of a first semiconductor chip, second pads provided on the reverse side in a second region defined thereon and overlapping with the first region, and to be connected to terminals arranged on a surface of a second semiconductor chip, and interlayer wiring electrically connecting those of the first pads, which are located in an overlapping region, to those of the second pads which are located in the overlapping region.

Abstract translation: 根据一个实施例，印刷电路板包括：主体，其具有正面和正面布线层的正面;反面具有反面布线层，第一焊盘设置在其上限定的第一区域的正面上，并且为 连接到布置在第一半导体芯片的表面上的端子，在限定在其上并与第一区域重叠的第二区域中的反面上设置的第二焊盘，并且连接到布置在第二半导体芯片的表面上的端子，以及 将位于重叠区域中的第一焊盘电连接到位于重叠区域中的第二焊盘的层间布线。

公开(公告)号：US20080271914A1

公开(公告)日：2008-11-06

申请号：US12168508

申请日：2008-07-07

Applicant: Makoto Tanaka ,  Yuichi Koga

Inventor： Makoto Tanaka ,  Yuichi Koga

IPC: H05K1/11

CPC classification number: G06F1/1616 ,  G06F1/1656 ,  G06F1/18 ,  H01L2224/16225 ,  H01L2924/10158 ,  H01L2924/15311 ,  H05K1/114 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2203/1572 ,  Y02P70/611

Abstract: According to one embodiment, a printed wiring board includes, a main body including an obverse side with an obverse wiring layer, and a reverse side with a reverse wiring layer first pads provided on the obverse side in a first region defined thereon, and to be connected to terminals arranged on a surface of a first semiconductor chip, second pads provided on the reverse side in a second region defined thereon and overlapping with the first region, and to be connected to terminals arranged on a surface of a second semiconductor chip, and interlayer wiring electrically connecting those of the first pads, which are located in an overlapping region, to those of the second pads which are located in the overlapping region.

Abstract translation: 根据一个实施例，印刷电路板包括：主体，其具有正面和正面布线层的正面;反面具有反面布线层，第一焊盘设置在其上限定的第一区域的正面上，并且为 连接到布置在第一半导体芯片的表面上的端子，在限定在其上并与第一区域重叠的第二区域中的反面上设置的第二焊盘，并且连接到布置在第二半导体芯片的表面上的端子，以及 将位于重叠区域中的第一焊盘电连接到位于重叠区域中的第二焊盘的层间布线。

公开(公告)号：US20080267556A1

公开(公告)日：2008-10-30

申请号：US12166442

申请日：2008-07-02

Applicant: John R. Dangler ,  Matthew S. Doyle

Inventor： John R. Dangler ,  Matthew S. Doyle

IPC: G02B6/12

CPC classification number: G02B6/3608 ,  G02B6/3688 ,  H05K1/02 ,  H05K1/0393 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536

Abstract: A flexible printed circuit capable of transmitting electrical and optical signals is disclosed. The flexible printed circuit includes a set of optical waveguides for transmitting optical signals and a set of conductors for transmitting electrical signals. Each of a subset of the optical waveguides is enclosed by a respectively one of the conductors. The optical waveguide is made of glass or plastic. The conductors are formed within a first building block constructed by a first dielectric layer and a first substrate layer, and a second building block constructed by a second dielectric layer and a second substrate layer.

Abstract translation: 公开了能够发送电和光信号的柔性印刷电路。 柔性印刷电路包括用于传输光信号的一组光波导和用于传输电信号的一组导体。 光波导的一个子集中的每一个被分别由一个导体包围。 光波导由玻璃或塑料制成。 导体形成在由第一介电层和第一基底层构成的第一构建块内，以及由第二介电层和第二基底层构成的第二构建块。

公开(公告)号：US20080250377A1

公开(公告)日：2008-10-09

申请号：US11696659

申请日：2007-04-04

Applicant: Steven C. Bird ,  Varoujan Malian ,  Mudasir Ahmad ,  Charles H. Casale ,  Danlu Tang

Inventor： Steven C. Bird ,  Varoujan Malian ,  Mudasir Ahmad ,  Charles H. Casale ,  Danlu Tang

IPC: G06F17/50 ,  G01R31/00

CPC classification number: G01R31/2818 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/0262 ,  H05K1/0268 ,  H05K1/113 ,  H05K1/181 ,  H05K3/3421 ,  H05K3/3457 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/0367 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/09663 ,  H05K2201/10333 ,  H05K2201/10462 ,  H05K2201/10484 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: Methods and apparatus for accessing a high speed signal routed on a conductive trace on an internal layer of a printed circuit board (PCB) using high density interconnect (HDI technology) are provided. The conductive trace may be coupled to a microvia (μVia) having a conductive dome disposed above the outer layer pad of the μVia. In-circuit test (ICT) fixtures or high speed test probes may interface with the conductive dome to test the high speed signal with decreased reflection loss and other parasitic effects when compared to conventional test points utilizing plated through-hole (PTH) technology.

Abstract translation: 提供了使用高密度互连（HDI技术）访问在印刷电路板（PCB）的内层上的导电迹线上路由的高速信号的方法和装置。 导电迹线可以耦合到具有设置在muVia的外层焊盘上方的导电圆顶的微孔（muVia）。 与使用电镀通孔（PTH）技术的常规测试点相比，在线测试（ICT）固定装置或高速测试探头可与导电圆顶接口以测试具有降低的反射损耗和其他寄生效应的高速信号。

公开(公告)号：US20080238568A1

公开(公告)日：2008-10-02

申请号：US11729558

申请日：2007-03-29

Applicant: Emile Davies-venn ,  Telesphor Kamgaing

Inventor： Emile Davies-venn ,  Telesphor Kamgaing

IPC: H03H7/42

CPC classification number: H03H7/42 ,  H03H2001/0085 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536

Abstract: Methods and apparatus relating to package embedded three dimensional baluns are described. In one embodiment, components of one or more baluns may be embedded in a single semiconductor substrate. Other embodiments are also described.

Abstract translation: 描述了与封装嵌入式三维巴伦相关的方法和装置。 在一个实施例中，一个或多个巴伦的组件可以嵌入在单个半导体衬底中。 还描述了其它实施例。

公开(公告)号：US20080189943A1

公开(公告)日：2008-08-14

申请号：US12098582

申请日：2008-04-07

Applicant: Naohiro HIROSE ,  Kouta Noda ,  Hiroshi Segawa ,  Honjin En ,  Kiyotaka Tsukada ,  Naoto Ishida ,  Kouji Asano ,  Atsushi Shouda

Inventor： Naohiro HIROSE ,  Kouta Noda ,  Hiroshi Segawa ,  Honjin En ,  Kiyotaka Tsukada ,  Naoto Ishida ,  Kouji Asano ,  Atsushi Shouda

IPC: H05K3/42 ,  H01L21/306

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 μm) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.

Abstract translation: 通过激光束在树脂20中形成开口，从而形成通孔。 此时，通过进行蚀刻来降低导热率的铜箔22的厚度（3μm）被用作保形掩模。 因此，如果脉冲形激光束的照射次数减少，则可以在树脂20中形成开口部20a。 因此，可以防止形成层间绝缘树脂层的树脂20的底切的发生。 因此，可以提高通孔连接的可靠性。

公开(公告)号：US07408261B2

公开(公告)日：2008-08-05

申请号：US10969403

申请日：2004-10-20

Applicant: Kyoung-Ro Yoon ,  Young-Hwan Shin ,  Tae-Gon Lee

Inventor： Kyoung-Ro Yoon ,  Young-Hwan Shin ,  Tae-Gon Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K3/243 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H05K3/061 ,  H05K3/28 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/09736 ,  H05K2203/0353 ,  H05K2203/0574 ,  H05K2203/0577 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Disclosed herein is a Ball Grid Array (BGA) package board. The BGA package board includes a first external layer on which a pattern comprising a circuit pattern and a wire bonding pad pattern is formed, a second external layer on which a pattern comprising a circuit pattern and a solder ball pad pattern is formed, an insulating layer formed between the first and second external layers, a first outer via hole to electrically connect the first and second external layers to each other, and a solder resist layer formed on each of the first and second external layers, with portions of the solder resist layer corresponding to the wire bonding pad pattern and the solder ball pad pattern being opened. The solder ball pad pattern is thinner than the circuit pattern of the second external layer.

Abstract translation: 本文公开了一种球栅阵列（BGA）封装板。 BGA封装板包括：第一外层，其上形成包括电路图案和引线焊盘图案的图案;第二外层，其上形成包括电路图案和焊球图案的图案;绝缘层 形成在第一和第二外部层之间的第一外部通孔，用于将第一和第二外部层彼此电连接的第一外部通孔，以及形成在第一和第二外部层中的每一个上的阻焊层，其中阻焊层的一部分 对应于引线焊盘图案和焊球图案打开。 焊球焊盘图案比第二外层的电路图形薄。

公开(公告)号：US20080173473A1

公开(公告)日：2008-07-24

申请号：US11875486

申请日：2007-10-19

Applicant: Naohiro HIROSE ,  Kouta Noda ,  Hiroshi Segawa ,  Honjin En ,  Kiyotaka Tsukada ,  Naoto Ishida ,  Kouji Asano ,  Atsushi Shouda

Inventor： Naohiro HIROSE ,  Kouta Noda ,  Hiroshi Segawa ,  Honjin En ,  Kiyotaka Tsukada ,  Naoto Ishida ,  Kouji Asano ,  Atsushi Shouda

IPC: H01R12/04

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 μm) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.

Abstract translation: 通过激光束在树脂20中形成开口，从而形成通孔。 此时，通过进行蚀刻来降低导热率的铜箔22的厚度（3μm）被用作保形掩模。 因此，如果脉冲形激光束的照射次数减少，则可以在树脂20中形成开口部20a。 因此，可以防止形成层间绝缘树脂层的树脂20的底切的发生。 因此，可以提高通孔连接的可靠性。