公开(公告)号：US07339269B2

公开(公告)日：2008-03-04

申请号：US10220409

申请日：2001-11-19

Applicant: Hiroaki Matsuki ,  Masayoshi Shouno ,  Tomohiko Tamaki

Inventor： Hiroaki Matsuki ,  Masayoshi Shouno ,  Tomohiko Tamaki

IPC: H01L23/34

CPC classification number: H05K1/0231 ,  H01L23/642 ,  H01L23/66 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32188 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0243 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A high frequency IC package and high frequency unit are simplified and downsized, and the number of manufacturing processes is reduced. The part 9 to determine a characteristic of the high frequency IC chip is arranged outside the sealing 14 of the high frequency IC package 5. The part can be arranged on the package board 7, circuit board 4 or housing chassis 1. When the part is arranged outside the sealing, the package and the high frequency unit 6 on which the package is mounted can be downsized. In the case of arranging the part on the circuit board, the part can be mounted together with other surface mounting parts. Therefore, the number of manufacturing processes can be reduced.

Abstract translation: 高频IC封装和高频单元被简化和小型化，并且制造工艺的数量减少。 确定高频IC芯片的特性的部分9设置在高频IC封装5的密封14的外部。 该部件可以布置在封装板7，电路板4或外壳底盘1上。 当部件布置在密封件外部时，封装件和安装有封装件的高频单元6可以被小型化。 在将部件布置在电路板上的情况下，部件可以与其他表面安装部件一起安装。 因此，可以减少制造工序的数量。

公开(公告)号：US07298040B2

公开(公告)日：2007-11-20

申请号：US11177700

申请日：2005-07-08

Applicant: William P. Cornelius

Inventor： William P. Cornelius

IPC: H01L23/498

CPC classification number: H01L24/48 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/645 ,  H01L24/06 ,  H01L24/45 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/49052 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/112 ,  H05K2201/10545 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Wire bonding methods and apparatuses are described herein. In one aspect of the invention, an exemplary apparatus includes a plurality of electrically conductive contacts disposed on a surface of the IC device, the plurality of electrically conductive contacts being disposed in at least two rows, a plurality of first return paths formed through some of the plurality of electrically conductive contacts, a plurality of signal paths formed through some of the plurality of electrically conductive contacts, and wherein at least one of the plurality of first return paths are placed between every predetermined number of the plurality of the signal-paths. Other methods and apparatuses are also described.

Abstract translation: 引线接合方法和装置在本文中描述。 在本发明的一个方面，示例性装置包括设置在IC器件的表面上的多个导电触头，多个导电触点设置在至少两行中，多个第一返回路径通过一些 所述多个导电触点，通过所述多个导电触点中的一些形成的多个信号路径，并且其中所述多个第一返回路径中的至少一个被放置在所述多个信号路径的每个预定数量之间。 还描述了其它方法和装置。

公开(公告)号：US07269025B2

公开(公告)日：2007-09-11

申请号：US11026606

申请日：2004-12-30

Applicant: Howard David

Inventor： Howard David

IPC: H05K7/00

CPC classification number: H05K1/181 ,  G11C5/04 ,  H01L23/50 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/09701 ,  H05K1/112 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: In some embodiments, a multichip package includes mounting pads to mount devices, such as integrated circuits, to a substrate, such as a printed circuit board, so that devices mutually placed on opposite surfaces of the substrate do not have interfering connections or connection vias. Other embodiments are described.

Abstract translation: 在一些实施例中，多芯片封装包括用于将诸如集成电路的器件安装到衬底（例如印刷电路板）的安装焊盘，使得相互放置在衬底的相对表面上的器件不具有干涉连接或连接通孔。 描述其他实施例。

公开(公告)号：US20070158802A1

公开(公告)日：2007-07-12

申请号：US11434964

申请日：2006-05-16

Applicant: James Wehrly

Inventor： James Wehrly

IPC: H01L23/02 ,  H01L21/48

CPC classification number: H01L25/105 ,  G06K19/07732 ,  H01L23/5387 ,  H01L23/5388 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/189 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2201/2018 ,  H01L2924/00

Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allow the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.

Abstract translation: 本发明提供了一种在存储卡中采用引线封装的存储器件的系统和方法。 引线封装IC布置在柔性电路结构的一侧或两侧以产生IC填充结构。 在优选实施例中，构成引线IC封装的引线被配置为允许引线IC封装的下表面接触柔性电路结构的相应表面。 用于典型实施例的触头由柔性电路结构的刚性部分支撑，并且IC填充结构设置在壳体中以为模块提供卡结构。

公开(公告)号：US20070144770A1

公开(公告)日：2007-06-28

申请号：US11376331

申请日：2006-03-16

Applicant: Tomoyuki Nakao

Inventor： Tomoyuki Nakao

IPC: H05K1/16

CPC classification number: H05K1/0231 ,  H05K1/0225 ,  H05K1/0298 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/10545 ,  H05K2201/10689

Abstract: A first power supply layer spreads over an insulating layer outside an island of a second power supply layer. A first ground layer spreads over an insulating layer outside an island of a second ground layer. First and second electrically-conductive pieces are interposed between the first and second power supply layers as well as between the first and second ground layers. A capacitor is interposed between the first and second electrically-conductive pieces. Power supply noise is forced to inevitably pass through the electrically-conductive pieces. The power supply noise thus reliably flows into the capacitor through the first and second electrically-conductive pieces. A printed wiring board is in this manner allowed to enjoy a sufficient suppression of the power supply noise.

Abstract translation: 第一电源层在第二电源层的岛外面的绝缘层上铺展。 第一接地层扩散在第二接地层的岛外的绝缘层上。 第一和第二导电片插入在第一和第二电源层之间以及第一和第二接地层之间。 在第一和第二导电片之间插入电容器。 电源噪声被迫不可避免地穿过导电片。 因此，电源噪声通过第一导电片和第二导电片可靠地流入电容器。 以这种方式允许印刷电路板充分抑制电源噪声。

公开(公告)号：US20070115712A1

公开(公告)日：2007-05-24

申请号：US11654435

申请日：2007-01-16

Applicant: Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

Inventor： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

IPC: G11C5/06

CPC classification number: H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

Abstract: The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

Abstract translation: 本发明涉及一种用于形成微电子存储器件的系统，模块以及装置和方法。 在一个实施例中，系统包括处理器和耦合到处理器的控制器，其中至少一个存储器模块耦合到控制器，该模块包括一对存储器件，其相对地定位在衬底的相应表面上并且通过延伸穿过 耦合器件的端子的基板，所述端子被选择为包括被配置为传送功能兼容的信号的一组端子。

公开(公告)号：US07190069B2

公开(公告)日：2007-03-13

申请号：US09970145

申请日：2001-10-02

Applicant: Nick A. Youker ,  Ronald L. Anderson ,  John E. Hansen

Inventor： Nick A. Youker ,  Ronald L. Anderson ,  John E. Hansen

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/14

CPC classification number: H05K1/189 ,  A61N1/375 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/113 ,  H05K3/4069 ,  H05K2201/10545 ,  H05K2201/10681 ,  H01L2924/00

Abstract: A tape automated bonding (TAB) structure which includes a flex tape having a conductive lead pattern formed thereon. The conductive lead pattern includes a plurality of leads configured to form an inner lead bond (ILB) portion of the TAB structure. At least one of the plurality of leads is internally routed and has a contact exposed interior to the ILB portion of the TAB structure.

Abstract translation: 一种胶带自动接合（TAB）结构，其包括在其上形成导电图案的柔性带。 导电引线图形包括多个引线，其被配置为形成TAB结构的内部引线键合（ILB）部分。 所述多个引线中的至少一个在内部布线并且具有暴露在TAB结构的ILB部分内部的触点。

公开(公告)号：US07153723B1

公开(公告)日：2006-12-26

申请号：US10727386

申请日：2003-12-04

Applicant: Earl Medeiros

Inventor： Earl Medeiros

IPC: H01L21/44

CPC classification number: H05K1/0231 ,  H01L21/485 ,  H01L23/49816 ,  H01L23/50 ,  H01L2924/0002 ,  H05K3/429 ,  H05K2201/10545 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A method includes:A. providing a substrate having a first surface and a second surface, the first surface being adapted for mounting an electronic device thereon;B. forming a grid of electrically conductive vias extending from a region proximate the first surface to a region proximate the second surface, each via being one of a signal via, a ground via and a power via;C. removing at least one of the vias to form a void between at least one ground via and at least one power via; andD. connecting each of the at least one ground via proximate the void to one of the at least one power vias proximate the void with a filter device proximate the second surface of the substrate.

Abstract translation: 一种方法包括：A.提供具有第一表面和第二表面的基底，所述第一表面适于在其上安装电子装置; B.形成从靠近第一表面的区域延伸到靠近第二表面的区域的导电通孔格栅，每个通孔是信号通孔，接地通孔和电源通孔之一; 去除至少一个通孔以在至少一个接地通孔和至少一个电源通孔之间形成空隙; 以及D.将所述至少一个地面中的每一个通过邻近所述空隙连接到所述至少一个靠近所述空隙的所述至少一个电力通道中，并具有靠近所述基板的第二表面的过滤器装置。

公开(公告)号：US07145782B2

公开(公告)日：2006-12-05

申请号：US10892804

申请日：2004-07-16

Applicant: Damion Searls ,  Edward Osburn

Inventor： Damion Searls ,  Edward Osburn

IPC: H05K7/06 ,  H01L23/48

CPC classification number: H01L23/49844 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1531 ,  H01L2924/19106 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/0262 ,  H05K1/181 ,  H05K2201/1006 ,  H05K2201/10166 ,  H05K2201/10325 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10704 ,  Y10T29/4913 ,  Y10T29/49147 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.

公开(公告)号：US20060231912A1

公开(公告)日：2006-10-19

申请号：US11404771

申请日：2006-04-17

Applicant: Makoto Tanaka ,  Yuichi Koga

Inventor： Makoto Tanaka ,  Yuichi Koga

IPC: H01L31/00

CPC classification number: G06F1/1616 ,  G06F1/1656 ,  G06F1/18 ,  H01L2224/16225 ,  H01L2924/10158 ,  H01L2924/15311 ,  H05K1/114 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2203/1572 ,  Y02P70/611

Abstract: According to one embodiment, a printed wiring board includes, a main body including an obverse side with an obverse wiring layer, and a reverse side with a reverse wiring layer first pads provided on the obverse side in a first region defined thereon, and to be connected to terminals arranged on a surface of a first semiconductor chip, second pads provided on the reverse side in a second region defined thereon and overlapping with the first region, and to be connected to terminals arranged on a surface of a second semiconductor chip, and interlayer wiring electrically connecting those of the first pads, which are located in an overlapping region, to those of the second pads which are located in the overlapping region.

Abstract translation: 根据一个实施例，印刷电路板包括：主体，其具有正面和正面布线层的正面;反面具有反面布线层，第一焊盘设置在其上限定的第一区域的正面上，并且为 连接到布置在第一半导体芯片的表面上的端子，在限定在其上并与第一区域重叠的第二区域中的反面上设置的第二焊盘，并且连接到布置在第二半导体芯片的表面上的端子，以及 将位于重叠区域中的第一焊盘电连接到位于重叠区域中的第二焊盘的层间布线。