公开(公告)号：US06934160B2

公开(公告)日：2005-08-23

申请号：US10085302

申请日：2002-02-28

Applicant: Björn Heismann ,  Quirin Spreiter ,  Helmut Winkelmann

Inventor： Björn Heismann ,  Quirin Spreiter ,  Helmut Winkelmann

IPC: H05K1/18 ,  H01L21/60 ,  H01L23/40 ,  H01L23/498 ,  H01L31/02 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K1/112 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/48997 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/12043 ,  H01L2924/3025 ,  H05K1/189 ,  H05K3/4691 ,  H05K2201/09472 ,  H05K2203/049 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A printed circuit board arrangement with a flexible layer arrangement of at least one electrically conductive layer with a large number of conductor tracks lying next to one another and surrounded by electrically isolating layers has at least one printed circuit board firmly connected to a portion of the flexible layer arrangement and accommodating a component. To form a connection between the component and the conductor tracks of the flexible layer, an opening through the printed circuit board to the conductor tracks is provided, which opening may be stepped, so that different conductor tracks and different layers can be reached.

Abstract translation: 具有柔性层布置的印刷电路板布置具有至少一个具有彼此相邻并被电绝缘层包围的多个导体轨道的导电层的导电层，至少一个印刷电路板牢固地连接到柔性的一部分 层布置和容纳部件。 为了形成柔性层的部件和导体轨道之间的连接，提供通过印刷电路板到导体轨道的开口，该开口可以是阶梯状的，使得可以达到不同的导体轨迹和不同的层。

公开(公告)号：US06927490B2

公开(公告)日：2005-08-09

申请号：US10960411

申请日：2004-10-07

Applicant: Paul D. Franzon ,  Stephen E. Mick ,  John M. Wilson

Inventor： Paul D. Franzon ,  Stephen E. Mick ,  John M. Wilson

IPC: H01L23/13 ,  H01L23/48 ,  H01L23/498 ,  H05K1/02 ,  H05K1/16 ,  H05K3/34

CPC classification number: H01L24/73 ,  H01L23/13 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0239 ,  H05K1/0243 ,  H05K1/0263 ,  H05K1/165 ,  H05K3/3436 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/10727 ,  H01L2224/05599

Abstract: Microelectronic packages include a first microelectronic substrate having a first face and a first AC-coupled interconnect element on the first face. A second microelectronic substrate includes a second face and a second AC-coupled interconnect element on the second face. A buried solder bump extends between the first and second faces, and is at least partially buried beneath the first and/or second faces, to maintain the first and second AC-coupled interconnect elements in closely spaced apart relation. The buried solder bump also may couple DC power between the first and second substrates. Other technologies also may be used to maintain the AC-coupled interconnect elements in closely spaced apart relation and to couple DC power between the substrates. The first and second AC-coupled interconnect elements may be first and second capacitor plates, first and second inductors and/or first and second combined inductive and capacitive elements.

公开(公告)号：US20050164416A1

公开(公告)日：2005-07-28

申请号：US10973704

申请日：2004-10-26

Applicant: Douglas Ondricek ,  David Pederson

Inventor： Douglas Ondricek ,  David Pederson

IPC: G01R1/04 ,  G01R31/01 ,  G01R31/28 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/48 ,  H01L23/538 ,  H05K3/32 ,  H01L21/00 ,  G01R31/02 ,  G01R31/26 ,  H01L21/301 ,  H01L21/46 ,  H01L21/66 ,  H01L21/78

CPC classification number: G01R1/0466 ,  G01R1/0408 ,  G01R1/0433 ,  G01R31/01 ,  G01R31/2863 ,  G01R31/2867 ,  G01R31/2893 ,  H01L21/67294 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/5385 ,  H01L24/72 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/73251 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/16152 ,  H05K3/325 ,  H05K2201/09472 ,  H01L2924/00 ,  H01L2224/72

Abstract: Methods for processing at least one die which comprises an integrated circuit. In one example of a method of the invention, an identification code is applied to a carrier. A singulated die is deposited into the carrier which holds the singulated die. The singulated die comprises an integrated circuit. The identification code may be applied to the carrier before or after depositing the singulated die into the carrier. The carrier may be used in testing the singulated die and may include a plurality of singulated die or just one singulated die. In another example of a method of the invention, an identification code is applied to a die. The die is deposited into a carrier which holds the die. The die comprises an integrated circuit, and the carrier holds the die in singulated form. Typically the die is placed in the carrier without any packaging which may protect the die. The identification code may be applied to the die before or after it is deposited into the carrier.

Abstract translation: 用于处理包括集成电路的至少一个管芯的方法。 在本发明的方法的一个示例中，将识别码应用于载体。 单片模具沉积在保持单模模具的载体中。 单片模具包括集成电路。 可以在将分割的裸片沉积到载体中之前或之后将识别码应用于载体。 载体可以用于测试单个模具，并且可以包括多个单个模具或仅一个单模模具。 在本发明方法的另一个例子中，将识别码应用于管芯。 模具沉积在保持模具的载体中。 芯片包括集成电路，并且载体以单模形式保持模具。 通常，模具被放置在载体中而没有任何可保护模具的包装。 识别码可以在将其沉积到载体中之前或之后施加于该芯片。

公开(公告)号：US20050156326A1

公开(公告)日：2005-07-21

申请号：US11029676

申请日：2005-01-06

Applicant: Toshihide Ito

Inventor： Toshihide Ito

IPC: H01L23/12 ,  H01L21/48 ,  H01L21/56 ,  H01L21/68 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H05K1/11 ,  H05K3/20 ,  H05K3/46 ,  H01L21/44 ,  H01L23/053 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/568 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/11334 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/20 ,  H05K3/4614 ,  H05K2201/09036 ,  H05K2201/09472 ,  Y10T29/49165 ,  H01L2924/00

Abstract: To fabricate a semiconductor device, a pattern of recesses and lands is formed on a copper sheet as a matrix sheet, and BGA pads are formed on the lands on the copper sheet. An insulating layer is formed on the copper sheet to transfer the pattern of recesses and lands from the copper sheet to the insulating layer for thereby forming recesses in the insulating layer and placing BGA pads in the recesses in the insulating layer. Vias are formed through the insulating layer, and a conductive layer serving as circuits and interconnections is formed, the conductive layer being connected to the BGA pads by the vias. When the copper sheet is removed, the BGA pads are positioned within the recesses in the insulating layer. The BGA pads have surfaces positioned higher than the bottom of the recesses and lower than the surface of the insulating layer. A semiconductor chip is mounted on the conductive layer, and solder balls are joined to the BGA pads. Both the productivity of a process of mounting the solder balls and the bonding strength of the solder balls are increased.

Abstract translation: 为了制造半导体器件，在作为基质片的铜片上形成凹凸图案，并且在铜片上的焊盘上形成BGA焊盘。 在铜片上形成绝缘层，将凹凸的图案从铜片转移到绝缘层，从而在绝缘层中形成凹部，并将BGA焊盘放置在绝缘层的凹部中。 通过绝缘层形成通孔，并且形成用作电路和互连的导电层，导电层通过通孔连接到BGA焊盘。 当去除铜片时，BGA焊盘位于绝缘层的凹槽内。 BGA焊盘具有高于凹部底部的表面，并且比绝缘层的表面低。 半导体芯片安装在导电层上，焊球与BGA焊盘接合。 焊球的安装工艺和焊球的接合强度都提高了生产效率。

公开(公告)号：US06896173B2

公开(公告)日：2005-05-24

申请号：US10710561

申请日：2004-07-21

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: B23K1/00 ,  B23K1/19 ,  B23K1/20 ,  H01L21/48 ,  H05K3/24 ,  H05K3/28 ,  B23K31/02

CPC classification number: H01L21/4857 ,  B23K1/0018 ,  B23K1/19 ,  B23K1/20 ,  B23K2101/42 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09881 ,  H05K2203/054 ,  H05K2203/0542

Abstract: The present invention provides a method of fabricating a circuit substrate. First, a substrate having first pads and second pads is provided, wherein the first pads and second pads are arranged respectively on a first surface and a second surface of the substrate. The first pads are electrically connected to the second pads. Next, a conductive seed layer is formed on the second surface of the circuit substrate. Thereafter, a first conductive layer and a second conductive layer are electroplated respectively over the first pads and the second pads. Afterwards, the conductive seed layer is patterned.

Abstract translation: 本发明提供一种制造电路基板的方法。 首先，提供具有第一焊盘和第二焊盘的衬底，其中第一焊盘和第二焊盘分别布置在衬底的第一表面和第二表面上。 第一焊盘电连接到第二焊盘。 接下来，在电路基板的第二表面上形成导电种子层。 此后，分别在第一焊盘和第二焊盘上电镀第一导电层和第二导电层。 之后，对导电种子层进行图案化。

公开(公告)号：US06885090B2

公开(公告)日：2005-04-26

申请号：US09997586

申请日：2001-11-28

Applicant: Paul D. Franzon ,  Stephen E. Mick ,  John M. Wilson

Inventor： Paul D. Franzon ,  Stephen E. Mick ,  John M. Wilson

IPC: H01L23/13 ,  H01L23/48 ,  H01L23/498 ,  H05K1/02 ,  H05K1/16 ,  H05K3/34 ,  H01L23/02

CPC classification number: H01L24/73 ,  H01L23/13 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0239 ,  H05K1/0243 ,  H05K1/0263 ,  H05K1/165 ,  H05K3/3436 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/10727 ,  H01L2224/05599

Abstract: Microelectronic packages include a first microelectronic substrate having a first face and a first AC-coupled interconnect element on the first face. A second microelectronic substrate includes a second face and a second AC-coupled interconnect element on the second face. A buried solder bump extends between the first and second faces, and is at least partially buried beneath the first and/or second faces, to maintain the first and second AC-coupled interconnect elements in closely spaced apart relation. The buried solder bump also may couple DC power between the first and second substrates. Other technologies also may be used to maintain the AC-coupled interconnect elements in closely spaced apart relation and to couple DC power between the substrates. The first and second AC-coupled interconnect elements may be first and second capacitor plates, first and second inductors and/or first and second combined inductive and capacitive elements.

Abstract translation: 微电子封装包括在第一面上具有第一面和第一AC耦合互连元件的第一微电子衬底。 第二微电子衬底包括在第二面上的第二面和第二AC耦合互连元件。 埋入的焊料凸块在第一和第二表面之间延伸，并且至少部分地埋在第一和/或第二表面之下，以将第一和第二AC耦合互连元件保持紧密间隔的关系。 埋入的焊料凸块还可以在第一和第二衬底之间耦合直流电力。 也可以使用其它技术来将交流耦合互连元件保持在紧密间隔的关系中并且在基板之间耦合直流电力。 第一和第二AC耦合互连元件可以是第一和第二电容器板，第一和第二电感器和/或第一和第二组合的电感和电容元件。

公开(公告)号：US20040256739A1

公开(公告)日：2004-12-23

申请号：US10893993

申请日：2004-07-20

Applicant: Seiko Epson Corporation

Inventor： Nobuaki Hashimoto

IPC: H01L021/48 ,  H01L023/52

CPC classification number: H01L24/29 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/83095 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83859 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/90 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/112 ,  H05K1/189 ,  H05K3/28 ,  H05K3/284 ,  H05K3/323 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10674 ,  H05K2203/0278 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05644

Abstract: A method of manufacturing a semiconductor device comprises: a first step of interposing a thermosetting anisotropic conductive material 16 between a substrate 12 and a semiconductor chip 20; a second step in which pressure and heat are applied between the semiconductor chip 20 and the substrate 12, an interconnect pattern 10 and electrodes 22 are electrically connected, and the anisotropic conductive material 16 is spreading out beyond the semiconductor chip 20 and is cured in the region of contact with the semiconductor chip 20; and a third step in which the region of the anisotropic conductive material 16 other than the region of contact with the semiconductor chip 20 is heated.

Abstract translation: 一种制造半导体器件的方法包括：在基板12和半导体芯片20之间插入热固性各向异性导电材料16的第一步骤; 在半导体芯片20和基板12之间施加压力和热量的第二步骤，布线图案10和电极22电连接，并且各向异性导电材料16扩散到半导体芯片20之外并在 与半导体芯片20的接触区域; 以及第三步骤，其中除了与半导体芯片20的接触区域之外的各向异性导电材料16的区域被加热。

公开(公告)号：US20040238970A1

公开(公告)日：2004-12-02

申请号：US10868066

申请日：2004-06-16

Applicant: Endicott Interconnect Technologies, Inc.

Inventor： David J. Alcoe

IPC: H01L023/48

CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/15312 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/116 ,  H05K3/3426 ,  H05K3/4602 ,  H05K2201/09454 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0979 ,  H05K2201/10318 ,  H01L2224/0401

Abstract: A circuitized substrate which utilizes an underlying conductive layer coupled to a pad on the substrate to assure a reinforced pad which will not be damaged or removed from the substrate when subjected to a significant load. Two or more pads can be similarly provided and coupled to the conductive layer, e.g., the layer being a common (ground) layer. An information handling system (e.g., a personal computer) utilizing the substrate is also provided.

Abstract translation: 电路化基板，其利用与基板上的焊盘耦合的下层导电层，以确保在经受显着载荷时不会损坏或从基板移除的加强垫。 可以类似地提供两个或更多个焊盘并耦合到导电层，例如该层是公共（接地）层。 还提供了利用该基板的信息处理系统（例如个人计算机）。

公开(公告)号：US20040226742A1

公开(公告)日：2004-11-18

申请号：US10437006

申请日：2003-05-14

Inventor： Aneta Wyrzykowska ,  Herman Kwong ,  Luigi Difilippo

IPC: H05K007/10

CPC classification number: H05K1/112 ,  H01L2224/14 ,  H01L2224/17 ,  H01L2924/00014 ,  H05K3/303 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/10318 ,  H05K2201/10424 ,  H05K2201/10659 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A method for implementing a circuit component on a surface of a multilayer circuit board is provided. The circuit component includes a plurality of pins and the circuit board includes a plurality of electrically conductive vias penetrating at least one layer of the circuit board and being arranged so as to form at least one channel for routing one or more traces at one or more signal layers of the circuit board. The method comprises the step of forming at least one pin of the plurality of pins of the circuit component to have a length compatible with a depth of a corresponding via of the circuit board.

Abstract translation: 提供一种在多层电路板的表面上实现电路元件的方法。 电路部件包括多个引脚，并且电路板包括穿透电路板的至少一个层的多个导电通孔，并被布置成形成用于在一个或多个信号处路由一个或多个迹线的至少一个通道 层的电路板。 该方法包括以下步骤：形成电路部件的多个引脚中的至少一个引脚以具有与电路板的相应通孔的深度相兼容的长度。

公开(公告)号：US20040223875A1

公开(公告)日：2004-11-11

申请号：US10861976

申请日：2004-06-04

Applicant: Medtronic MiniMed, Inc.

Inventor： Shaun Pendo ,  Rajiv Shah ,  Edward Chernoff

IPC: G01N021/00

CPC classification number: H05K3/28 ,  A61B5/0006 ,  H05K1/0306 ,  H05K3/4061 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2203/082 ,  H05K2203/085 ,  H05K2203/1147 ,  H05K2203/1476 ,  H05K2203/1572 ,  H05K2203/308

Abstract: A substrate with hermetically sealed vias extending from one side of the substrate to another and a method for fabricating same. The vias may be filled with a conductive material such as, for example, a fritless ink. The conductive path formed by the conductive material aids in sealing one side of the substrate from another. One side of the substrate may include a sensing element and another side of the substrate may include sensing electronics.

Abstract translation: 具有从衬底的一侧延伸到另一侧的气密密封通孔的衬底及其制造方法。 通孔可以填充有导电材料，例如无油墨。 由导电材料形成的导电路径有助于将基板的一侧与另一侧密封。 衬底的一侧可以包括感测元件，并且衬底的另一侧可以包括感测电子器件。