公开(公告)号：US07170012B2

公开(公告)日：2007-01-30

申请号：US11142399

申请日：2005-06-02

Applicant: Tokihito Suwa ,  Haruo Akahoshi ,  Shingo Kumamoto

Inventor： Tokihito Suwa ,  Haruo Akahoshi ,  Shingo Kumamoto

IPC: H05K1/09

CPC classification number: H05K3/44 ,  H05K1/115 ,  H05K3/4641 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/09663

Abstract: A multilayer circuit board including a laminate of at least one insulating layer and at least one wiring layer. The wiring layer is formed by a composite member having a first metal layer and a second metal layer formed on one or both sides of the first metal layer. The first metal layer having a smaller coefficient of thermal expansion than the second metal layer. The second metal layer having a higher electric conductivity than the first metal layer. The insulating layer has a blind via-hole with a bottom provided by a surface of the second metal layer. A layer-to-layer interconnection portion is provided on the surface of the insulating layer and in the blind via-hole and is formed in the blind via-hole to be in contact with the surface of the second metal layer.

Abstract translation: 包括至少一个绝缘层和至少一个布线层的叠层的多层电路板。 布线层由具有形成在第一金属层的一侧或两侧上的第一金属层和第二金属层的复合构件形成。 第一金属层的热膨胀系数小于第二金属层。 第二金属层的导电率比第一金属层高。 绝缘层具有通过第二金属层的表面设置的底部的盲通孔。 在绝缘层的表面和盲通孔中设置层间互连部，并且形成在盲通孔中，与第二金属层的表面接触。

公开(公告)号：US07148425B2

公开(公告)日：2006-12-12

申请号：US11043605

申请日：2005-01-26

Applicant: Tzong-Lin Wu ,  Yen-Hui Lin ,  Sin-Ting Chen ,  Ting-Kuang Wang

Inventor： Tzong-Lin Wu ,  Yen-Hui Lin ,  Sin-Ting Chen ,  Ting-Kuang Wang

IPC: H05K1/03

CPC classification number: H01L23/50 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H01L2924/00

Abstract: The invention relates to a power plane system for suppressing ground bounce noise. The power plane system of the invention comprises a substrate, a power layer and a ground layer. The power layer comprises a plurality of metal units. There is a distance between two adjacent metal units. A plurality of bridges is used for connecting the metal units. The ground layer has a grounding metal plate. According to the invention, when the ground bounce noise occurs, the metal units can broaden the stop-band bandwidth. Therefore, the signals in the stop-band hardly are transmitted so as to suppress the ground bounce noise, and the high frequency ground bounce noise and the electromagnetic radiation can be suppressed efficiently.

Abstract translation: 本发明涉及一种用于抑制地面反弹噪声的电力平面系统。 本发明的功率平面系统包括基板，功率层和接地层。 功率层包括多个金属单元。 两个相邻的金属单元之间有一段距离。 多个桥用于连接金属单元。 接地层有接地金属板。 根据本发明，当发生地面反弹噪声时，金属单元可以扩大阻带带宽。 因此，阻带中的信号几乎不发射，以抑制地面反弹噪声，并且可以有效地抑制高频地面反弹噪声和电磁辐射。

公开(公告)号：US20060255878A1

公开(公告)日：2006-11-16

申请号：US11489980

申请日：2006-07-20

Applicant: Samuel Babb ,  Erik Swanson ,  Lowell Kolb

Inventor： Samuel Babb ,  Erik Swanson ,  Lowell Kolb

IPC: H03H7/38

CPC classification number: H05K1/0216 ,  H01P3/08 ,  H05K1/0298 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09727

Abstract: A printed wiring board comprises a first plane having a split formed therein and at least one signal trace disposed on a second plane. The signal trace comprises an increased width in an area of the second plane corresponding to a location of the split.

Abstract translation: 印刷电路板包括其中形成有分裂的第一平面和设置在第二平面上的至少一个信号迹线。 信号迹线包括对应于分割位置的第二平面区域中增加的宽度。

公开(公告)号：US20060221585A1

公开(公告)日：2006-10-05

申请号：US11098951

申请日：2005-04-05

Applicant: Colin Brench

Inventor： Colin Brench

IPC: H05K7/06

CPC classification number: H05K1/0231 ,  H05K1/0227 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663

Abstract: Method and structure for modifying the boundary conditions between edges of adjacent or nearby split power planes in a circuit layout. The modified boundary conditions reduce coupling between the power planes, which reduces noise coupling between the power planes and allows for closer spacing between the power planes. In one embodiment the modified boundary conditions include a high impedance adjacent a low impedance.

Abstract translation: 用于修改电路布局中相邻或相邻分立电源平面边缘之间的边界条件的方法和结构。 改进的边界条件减少了电源层之间的耦合，这减小了电源层之间的噪声耦合，并允许电力平面之间的更紧密的间隔。 在一个实施例中，修改的边界条件包括邻近低阻抗的高阻抗。

公开(公告)号：US07102463B2

公开(公告)日：2006-09-05

申请号：US10160465

申请日：2002-05-30

Applicant: Clifford Clark

Inventor： Clifford Clark

IPC: H01P9/00

CPC classification number: H05K1/0216 ,  H05K1/023 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10022 ,  H05K2201/10689

Abstract: This invention relates to semiconductor devices and to printed circuit boards (PCB) or circuit assemblies used to electrically connect components. Delay devices are associated with the conductive traces or with integrated circuits. Delay is used to offset then realign the wave edges of propagating signals so as to minimize electric field effects on nearby signals. Impedance controlling devices are used to minimize reflections. The effects of split planes may be minimized or negated.

公开(公告)号：US07095623B2

公开(公告)日：2006-08-22

申请号：US10445000

申请日：2003-05-27

Applicant: Tokihito Suwa ,  Haruo Akahoshi ,  Shingo Kumamoto

Inventor： Tokihito Suwa ,  Haruo Akahoshi ,  Shingo Kumamoto

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K3/44 ,  H05K1/115 ,  H05K3/4641 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/09663

Abstract: A multilayer circuit board having a high level of reliability in terms of electric connection against temperature changes caused by the actual operation of electronic equipment, a manufacturing process, a substrate for multilayer circuitry, and an electronic apparatus. The multilayer circuit board comprises a laminate of at least one insulating layer and at least one wiring layer, wherein the wiring layer is formed by a composite member comprising a first metal layer and a second metal layer formed on one or both sides of the first metal layer, the first metal layer having a smaller coefficient of thermal expansion than the second metal layer, the second metal layer having a higher electric conductivity than the first metal layer, wherein the insulating layer has a blind via-hole with a bottom provided by a surface of the second metal layer, the circuit board further comprising a layer-to-layer interconnection portion on the surface of the insulating layer and in the blind via-hole, wherein the layer-to-layer interconnection portion in the blind via-hole is formed in such a manner as to be in contact with the surface of the second metal layer.

公开(公告)号：US07068518B2

公开(公告)日：2006-06-27

申请号：US09805250

申请日：2001-03-14

Applicant: Osamu Ueno ,  Hitoshi Arakaki

Inventor： Osamu Ueno ,  Hitoshi Arakaki

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0231 ,  H01L2224/16225 ,  H01L2924/19105 ,  H05K1/0227 ,  H05K1/0234 ,  H05K1/112 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09663 ,  H05K2201/10022 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A circuit board device suppress with a small number of terminal elements unwanted irradiation originating between a power supply layer and a ground layer, even when a configuration of the power supply layer and the ground layer on the circuit board is complex, and a design support device thereof. The circuit board device has a power supply layer and a ground layer disposed in opposition to one another. A dielectric is disposed between the power supply layer and the ground layer. A power supply surface is divided into two power supply surfaces and by a slit having a generally T-shaped configuration to form power supply surface edges. The power supply surface edges retain across a predetermined length L a characteristic impedance present between the power supply layer and the ground layer. A terminal load is connected to a terminal portion of the power supply surface edges.

Abstract translation: 电路板装置即使在电源层和电路板上的接地层的配置复杂的情况下也抑制少量端子元件产生电源层和接地层之间的不需要的照射，并且设计支持装置 其中。 电路板装置具有彼此相对设置的电源层和接地层。 电介质设置在电源层和接地层之间。 电源表面被分成两个电源表面和通常具有大致T形构造的狭缝以形成电源表面边缘。 电源表面边缘在预定长度L之间保持存在于电源层和接地层之间的特征阻抗。 端子负载连接到电源表面边缘的端子部分。

公开(公告)号：US06992376B2

公开(公告)日：2006-01-31

申请号：US10623073

申请日：2003-07-17

Applicant: Edward W. Jaeck

Inventor： Edward W. Jaeck

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/52 ,  H01L23/34 ,  H05K7/06

CPC classification number: H05K1/0281 ,  H01L23/5387 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/189 ,  H05K2201/0311 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09781 ,  H05K2201/2009 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic package of the kind having a folded substrate is provided. The substrate is configured so that a stress concentration is created where folding is desired. In the present example, the stress concentration is created with first a resilient metal ground layer that resists bending and has an edge that promotes the creation of a stress concentration in a flexible layer at or near the edge. A second metal ground layer resists bending in another portion of the substrate, and also has an edge creating a stress concentration in a different area of the flexible layer. The portions of the substrate having the first and second resilient metal ground layers can be folded over one another with substantially no bending in these portions, while a fold portion between the edges bends to allow for folding of the substrate.

公开(公告)号：US06989969B2

公开(公告)日：2006-01-24

申请号：US10963704

申请日：2004-10-13

Applicant: Tatsumi Tsuchiya ,  Yuhsuke Matsumoto ,  Takaaki Murokawa ,  Naoki Fujii ,  Takuya Satoh ,  Yasuhiro Mita ,  Hiroyasu Tsuchida ,  Yoshio Uematsu

Inventor： Tatsumi Tsuchiya ,  Yuhsuke Matsumoto ,  Takaaki Murokawa ,  Naoki Fujii ,  Takuya Satoh ,  Yasuhiro Mita ,  Hiroyasu Tsuchida ,  Yoshio Uematsu

IPC: G11B21/22 ,  G11B5/54 ,  H05K1/11

CPC classification number: G11B5/4853 ,  G11B5/484 ,  G11B5/486 ,  H01L2224/742 ,  H05K1/189 ,  H05K3/3442 ,  H05K3/3494 ,  H05K2201/0397 ,  H05K2201/09663 ,  H05K2201/09745 ,  H05K2203/041 ,  H05K2203/107 ,  H05K2203/159 ,  Y02P70/613 ,  Y10T29/49025 ,  Y10T29/4903 ,  Y10T29/49032 ,  Y10T29/49046 ,  Y10T29/49144 ,  Y10T29/49179

Abstract: An integrated lead suspension includes a solder ball that is placed between a lead wiring pad provided on a flexure of the suspension, and a bonding pad provided on a slider of a head gimbal section. The lead wiring pad and bonding pad are soldered by melting the solder ball. As a result, there is provided a recessed section into which a solder ball is placed by way of surface raised sections, using gravitational force, in the vicinity of the center line of the surface of the lead wiring pad. In this way the position of the solder ball is not displaced from the center line when a bonding pad and lead wiring pad are connected by means of a solder ball.

公开(公告)号：US20050286210A1

公开(公告)日：2005-12-29

申请号：US10533524

申请日：2004-04-09

Applicant: Hideki Ishida ,  Eizo Fujii ,  Yasuhiro Kishimoto ,  Hitoshi Ibuta

Inventor： Hideki Ishida ,  Eizo Fujii ,  Yasuhiro Kishimoto ,  Hitoshi Ibuta

IPC: H01G9/012 ,  H01G9/00 ,  H05K3/34 ,  H01G9/04

CPC classification number: H01G9/012 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: The present invention provides a solid electrolytic capacitor comprising a capacitor element in which a dielectric coating layer and a cathode layer are sequentially formed on a surface of an anode element having an anode lead member planted on one end surface thereof, an anode terminal connected with the anode lead member, a platy cathode terminal mounting the capacitor element thereon and connected with the cathode layer, and an enclosure resin coating the capacitor element, a part of the cathode terminal and a part of the anode terminal being exposed on a same plane from the enclosure resin. The cathode terminal is provided with a cathode exposed portion exposed from the enclosure resin in at least two locations on the same plane.

Abstract translation: 本发明提供一种固体电解电容器，其包括电容器元件，其中在其一端表面上具有阳极引线构件的阳极元件的表面上依次形成电介质涂层和阴极层，阳极端子与 阳极引线构件，将电容器元件安装在其上并与阴极层连接的板状阴极端子，以及涂覆电容器元件的封装树脂，阴极端子的一部分和阳极端子的一部分在同一平面上从 外壳树脂。 阴极端子设置有在同一平面上的至少两个位置处从外壳树脂露出的阴极暴露部分。