公开(公告)号：US20080138973A1

公开(公告)日：2008-06-12

申请号：US12027106

申请日：2008-02-06

Applicant: Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

Inventor： Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

Abstract translation: 本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。 在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。 衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。 该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。 该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。 该方法然后包括用导电材料填充通道。

公开(公告)号：US20080113466A1

公开(公告)日：2008-05-15

申请号：US11973193

申请日：2007-10-05

Applicant: Soichi Moriya ,  Takeo Kawase ,  Mitsuaki Harada ,  Takehisa Saeki ,  Tomoyuki Okuyama ,  Hirofumi Hokari ,  Takashi Aoki

Inventor： Soichi Moriya ,  Takeo Kawase ,  Mitsuaki Harada ,  Takehisa Saeki ,  Tomoyuki Okuyama ,  Hirofumi Hokari ,  Takashi Aoki

IPC: H01L31/18

CPC classification number: H05K3/0044 ,  H01L21/481 ,  H01L23/49811 ,  H01L51/0541 ,  H01L51/055 ,  H01L2924/0002 ,  H01L2924/19107 ,  H01L2924/3011 ,  H05K3/002 ,  H05K3/0035 ,  H05K3/28 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/0126 ,  H05K2203/0195 ,  H05K2203/0221 ,  H05K2203/082 ,  H05K2203/087 ,  H05K2203/1105 ,  H05K2203/1189 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a contact hole includes forming a first conductive layer patterned so as to serve as an electrode or a wiring on a substrate, forming an insulation layer on the substrate and the first conductive layer, inserting a cutting instrument into the insulation layer at an angle to a surface of the insulation layer, the angle being in the range from #5#° to~ 80#°, and forming a tapered opening extending to the electrode or the wiring in the insulation layer by drawing out the cutting instrument.

Abstract translation: 形成接触孔的方法包括形成图案化以在基板上作为电极或布线的第一导电层，在基板上形成绝缘层和第一导电层，将切割仪器插入绝缘层中 与绝缘层的表面成一定角度，该角度在＃5°〜〜80°°的范围内，并且通过拉出切割器具形成延伸到绝缘层中的电极或布线的锥形开口。

公开(公告)号：US20080087986A1

公开(公告)日：2008-04-17

申请号：US11986998

申请日：2007-11-27

Applicant: Ravindra Tanikella

Inventor： Ravindra Tanikella

IPC: H01L23/532 ,  H01L23/52

CPC classification number: H01L23/49894 ,  C08F283/04 ,  C08G73/121 ,  C08K3/36 ,  C08K9/10 ,  C08K2201/011 ,  C08L79/08 ,  C08L2666/66 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15791 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/28 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/1163 ,  H05K2203/121 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.

Abstract translation: 用于微电子封装的高度可靠的互连。 在一个实施例中，积聚互连中的电介质层具有玻璃化转变温度的等级; 并且稍后施加的电介质层在低于较早施加的电介质层的玻璃化转变温度的温度下被层压。 在一个实施方案中，通过热固化工艺增加了积聚互连中早期施加的介电膜的玻璃化转变温度，以超过用于层压后来施加的电介质膜的温度。 在一个实施方案中，在层压聚酰亚胺材料的膜（例如，通过催化剂的密封剂的光化学或热降解）之后，用嵌入的催化剂形成聚酰亚胺材料以促进交联。 在一个实施例中，阻焊剂开口壁具有通过激光辅助接种产生的可湿性层，使得阻焊剂开口壁之间没有间隙，并且在阻焊剂开口中没有底部填充物。

公开(公告)号：US20080022523A1

公开(公告)日：2008-01-31

申请号：US11868148

申请日：2007-10-05

Applicant: Alan Wang ,  Kevin Olson

Inventor： Alan Wang ,  Kevin Olson

IPC: H05K3/00 ,  H01K3/10

CPC classification number: H05K3/445 ,  H01L2224/16225 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/426 ,  H05K3/44 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0129 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/09154 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2201/09645 ,  H05K2201/09827 ,  H05K2203/1105 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit board includes an electrically conductive sheet having an insulative coating surrounding the conductive sheet, with a surface of the insulative coating around an edge of the conductive sheet having an arcuate or rounded shape. At least one electrical conductor is conformally deposited on at least the rounded insulative coating around the edge of the conductive sheet and defined via photolithographic and metallization techniques. Each electrical conductor on the insulative coating thereon around the edge of the conductive sheet conforms to the arcuate or rounded shape of the insulative coating and, therefore, has an arcuate or rounded shape.

Abstract translation: 电路板包括具有围绕导电片的绝缘涂层的导电片，绝缘涂层的表面围绕导电片的边缘具有弓形或圆形形状。 至少一个电导体被共形沉积在导电片的边缘周围的至少圆形绝缘涂层上，并通过光刻和金属化技术限定。 导电片边缘周围的绝缘涂层上的每个电导体符合绝缘涂层的弧形或圆形形状，因此具有弓形或圆形形状。

公开(公告)号：US20070290327A1

公开(公告)日：2007-12-20

申请号：US11765138

申请日：2007-06-19

Applicant: Mayumi Nakasato ,  Hideki Mizuhara

Inventor： Mayumi Nakasato ,  Hideki Mizuhara

IPC: H01L23/04

CPC classification number: H01L23/142 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/16225 ,  H05K3/427 ,  H05K3/445 ,  H05K2201/0355 ,  H05K2201/0382 ,  H05K2201/09827 ,  H05K2203/0143 ,  H05K2203/068 ,  Y10T29/49155

Abstract: The deterioration of dielectric breakdown strength arising from an opening of a metal plate is prevented and the reliability as a circuit board is enhanced. A circuit board is provided with a metal plate, having openings, as core material. The opening is provided in a manner that the size of the opening gradually increases from a lower surface side toward an upper surface side of the metal plate. On both surface sides of the metal plate there are provided wiring patterns, respectively, via insulating layers. The insulating layer provided on an upper region of the opening and the corresponding wiring pattern are provided such that they have a recess on the upper surface of them. To electrically connect each wiring pattern, the circuit board further includes a conductor which penetrates the metal plate via the opening and which connects the wiring patterns with each other. An LSI chip is directly coupled to the upper surface side of the metal plate via a solder ball.

Abstract translation: 防止由金属板的开口引起的介电击穿强度的劣化，并提高作为电路板的可靠性。 电路板设置有具有作为芯材料的开口的金属板。 开口以从金属板的下表面侧向上表面侧逐渐增大的方式设置。 在金属板的两个表面侧，分别经由绝缘层设置布线图案。 设置在开口的上部区域上的绝缘层和相应的布线图案设置成使得它们在其上表面上具有凹部。 为了电连接每个布线图案，电路板还包括经由开口穿过金属板并将布线图案彼此连接的导体。 LSI芯片通过焊球直接耦合到金属板的上表面侧。

公开(公告)号：US20070271783A1

公开(公告)日：2007-11-29

申请号：US11832378

申请日：2007-08-01

Applicant: Tomoyuki IKEDA

Inventor： Tomoyuki IKEDA

IPC: H05K3/46

CPC classification number: H01L23/50 ,  B32B3/10 ,  B32B7/02 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/3011 ,  H05K1/115 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09827 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multilayer core board 10 includes tapered first via hole conductors 51 extending from the outer surface of a first insulating layer 24 to conductive portions 42a of a power source layer 42, second via hole conductors 52 extending from the outer surface of a second insulating layer 26 to the conductive portions 42a of the power source layer 42, tapered third via hole conductors 53 extending from the outer surface of the second insulating layer 26 to conductive portions 40a of a ground layer 40, and fourth via hole conductors 54 extending from the outer surface of a center insulating layer 22 to the conductive portions 40a of the ground layer 40. The first via hole conductors 51 are tapered, and thus the interval distance to the adjacent first via hole conductor 51 is shorter than straight-shaped first via hole conductors, and thus the pitch of the first via hole conductor 51 at the positive pole side and the fourth via hole conductor 54 at the negative pole side can be sufficiently reduced. This point is applicable to the third via hole conductors 53.

Abstract translation: 多层芯板10包括从第一绝缘层24的外表面延伸到电源层42的导电部分42a的锥形第一通孔导体51，从第二绝缘层的外表面延伸的第二通孔导体52 26连接到电源层42的导电部分42,4a，从第二绝缘层26的外表面延伸到接地层40的导电部分40a的锥形第三通孔导体53以及从第二绝缘层40延伸的第四通孔导体54 中心绝缘层22的外表面连接到接地层40的导电部分40a。 第一通孔导体51是锥形的，因此到相邻的第一通路孔导体51的间隔距离比直线状的第一通孔导体短，因此第一通孔导体51在正极侧的间距和 可以充分降低负极侧的第四通孔导体54。 这点适用于第三通孔导体53。

公开(公告)号：US07284323B2

公开(公告)日：2007-10-23

申请号：US10711863

申请日：2004-10-11

Applicant: David C. H. Cheng

Inventor： David C. H. Cheng

IPC: H01K3/10

CPC classification number: H05K3/0047 ,  H05K3/0032 ,  H05K3/423 ,  H05K3/427 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T29/49156 ,  Y10T29/49167

Abstract: A fabrication process of a conductive column suitable for a fabrication of a circuit board. The circuit board comprises a dielectric layer. A first blind hole is formed in the dielectric layer from a second surface opposite to the first surface, wherein the blind end of the first blind hole connects to the blind end of the second blind hole. The first blind hole and the second blind hole constitute a through hole. The through hole is formed in an hourglass shape such that an inner diameter of the through hole near the first or the second surface is substantially larger than an inner diameter of the through hole near a middle portion of the through hole. A conductive material is filled in the though hole to form a conductive column.

Abstract translation: 适用于制造电路板的导电柱的制造工艺。 电路板包括电介质层。 从与第一表面相对的第二表面在电介质层中形成第一盲孔，其中第一盲孔的盲端连接到第二盲孔的盲端。 第一个盲孔和第二个盲孔构成一个通孔。 通孔形成为沙漏形状，使得在第一或第二表面附近的通孔的内径基本上大于通孔的中间部分附近的通孔的内径。 导电材料填充在通孔中以形成导电柱。

公开(公告)号：US20070132088A1

公开(公告)日：2007-06-14

申请号：US11580928

申请日：2006-10-16

Applicant: Takashi Kariya ,  Hironori Tanaka

Inventor： Takashi Kariya ,  Hironori Tanaka

IPC: H01L23/04

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09827 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2224/05599

Abstract: A printed circuit board including a conductor portion, an insulating layer formed over the conductor portion, a thin-film capacitor formed over the insulating layer and including a first electrode, a second electrode and a high-dielectric layer interposed between the first electrode and the second electrode, and a via-hole conductor structure formed through the second electrode and insulating layer and electrically connecting the second electrode and the conductor portion. The via-hole conductor structure has a first portion in the second electrode and a second portion in the insulating layer. The first portion of the via-hole conductor structure has a truncated-cone shape tapering toward the conductor portion.

Abstract translation: 一种印刷电路板，包括导体部分，在导体部分上形成的绝缘层，形成在绝缘层之上的薄膜电容器，并且包括第一电极，第二电极和介于第一电极和第二电极之间的高电介质层 第二电极和通过第二电极和绝缘层形成的通孔导体结构，并且电连接第二电极和导体部分。 通孔导体结构在第二电极中具有第一部分，在绝缘层中具有第二部分。 通孔导体结构的第一部分具有朝向导体部分逐渐变细的截锥形。

公开(公告)号：US20070096328A1

公开(公告)日：2007-05-03

申请号：US11480824

申请日：2006-07-06

Applicant: Michimasa Takahashi ,  Yukinobu Mikado ,  Takenobu Nakamura ,  Masakazu Aoyama

Inventor： Michimasa Takahashi ,  Yukinobu Mikado ,  Takenobu Nakamura ,  Masakazu Aoyama

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/48 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/00 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09709 ,  H05K2201/09827 ,  Y10T29/49124 ,  H01L2924/00

Abstract: A multilayer printed wiring board comprises a plurality of insulating layers which is about 100 μm or less in thickness and a plurality of conductor circuits formed on the insulating layers. Each of a plurality of viaholes electrically connecting conductor circuits on the insulating layers to each other is formed tapered inwardly from the surface of the insulating layer and the viaholes are disposed opposite to each other to form a multistage stacked vias.

Abstract translation: 多层印刷线路板包括多个厚度为100μm以下的绝缘层和在绝缘层上形成的多个导体电路。 将绝缘层上的导体电路彼此电连接的多个通孔中的每一个从绝缘层的表面向内形成为锥形，并且通孔彼此相对设置以形成多级堆叠通孔。

公开(公告)号：US07211899B2

公开(公告)日：2007-05-01

申请号：US10336728

申请日：2003-01-06

Applicant: Osamu Taniguchi ,  Yasuo Yamagishi ,  Koji Omote

Inventor： Osamu Taniguchi ,  Yasuo Yamagishi ,  Koji Omote

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/15 ,  H01L23/481 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/0044 ,  H05K3/4605 ,  H05K2201/09827 ,  H05K2203/025

Abstract: A circuit substrate comprises a glass substrate 16, through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18. An opening width of the through-holes 18 is minimum inside the glass substrate and is increased toward both surfaces of the glass substrate 16. Accordingly, the detachment of the via electrodes 20 can be prevented without increasing the surface roughness of the inside walls of the through holes, and stresses generated in the core substrate can be mitigated.

Abstract translation: 电路基板包括玻璃基板16，通过玻璃基板16形成的通孔18和埋在通孔18中的通孔电极20。 通孔18的开口宽度在玻璃基板的内部是最小的，并且朝向玻璃基板16的两个表面增加。 因此，可以防止通孔电极20的分离，而不会增加通孔内壁的表面粗糙度，并且可以减轻芯基板中产生的应力。