-
公开(公告)号：US12044585B1
公开(公告)日：2024-07-23
申请号：US17320719
申请日：2021-05-14
Inventor： Robert S. Okojie
CPC classification number: G01L19/0092 , B81B7/0035 , B81C1/00158 , G01K7/16 , G01L9/06 , H01L29/66053 , B81B2201/0264 , B81B2201/0278 , B81C2201/0132 , B81C2201/0156 , B81C2201/0197
Abstract: An integration of silicon carbide (SiC) pressure sensor and a temperature sensor on a single SiC substrate to facilitate the simultaneous measurement of pressure and temperature at temperature, and a method of fabricating the same.
-
公开(公告)号：US20240158225A1
公开(公告)日：2024-05-16
申请号：US18075882
申请日：2022-12-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jung-Hao CHANG , Weng-Yi CHEN
CPC classification number: B81C1/00476 , B81B7/02 , B81B2201/0257 , B81B2203/0315 , B81B2203/033 , B81B2203/0353 , B81B2207/01 , B81C2201/0108 , B81C2201/0132 , B81C2201/0133 , B81C2201/014 , B81C2201/0176
Abstract: A micro electro mechanical system (MEMS) device and a method for manufacturing the same are provided. The MEMS device includes a substrate, a polymer film on the substrate and having a lower surface facing toward the substrate, a cavity passing through the substrate, and coil structures on the substrate and in the polymer film. The polymer film includes a corrugation pattern on the lower surface of the polymer film. A portion of the polymer film is exposed in the cavity.
-
公开(公告)号：US11851320B2
公开(公告)日：2023-12-26
申请号：US16609968
申请日：2018-05-01
Applicant: THE JOHNS HOPKINS UNIVERSITY
Inventor： Gi-Dong Sim , Jessica Krogstad , Timothy P. Weihs , Kevin J. Hemker , Gianna Valentino
CPC classification number: B81B3/0075 , B81C1/00674 , C23C14/18 , C23C14/5806 , C25D3/562 , C25D5/50 , B81B2203/0118 , B81C2201/0132 , B81C2201/0133 , B81C2201/0181 , B81C2201/0197
Abstract: The present invention is directed to the synthesis of metallic nickel-molybdenum-tungsten films and coatings with direct current sputter deposition, which results in fully-dense crystallographically textured films that are filled with nano-scale faults and twins. The as-deposited films exhibit linear-elastic mechanical behavior and tensile strengths above 2.5 GPa, which is unprecedented for materials that are compatible with wafer-level device fabrication processes. The ultra-high strength is attributed to a combination of solid solution strengthening and the presence of the dense nano-scale faults and twins. These films also possess excellent thermal and mechanical stability, high density, low CTE, and electrical properties that are attractive for next generation metal MEMS applications. Deposited as coatings these films provide protection against friction and wear. The as-deposited films can also be heat treated to modify the internal microstructure and attendant mechanical properties in a way that provides a desired balance of strength and toughness.
-
公开(公告)号：US20230278856A1
公开(公告)日：2023-09-07
申请号：US18315799
申请日：2023-05-11
Applicant: Taiwan Semiconductor manufacturing Co., Ltd.
Inventor： Yu-Chia Liu , Chia-Hua Chu , Chun-Wen Cheng
CPC classification number: B81B7/0006 , B81C1/00246 , B81B7/0051 , B81B2201/0264 , B81B2201/0271 , B81B2201/0257 , B81C2203/0714 , B81C2201/112 , B81C2201/0176 , B81C2201/0181 , B81C2201/0132 , B81C2201/0133 , B81C2203/0735
Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
-
公开(公告)号：US11708265B2
公开(公告)日：2023-07-25
申请号：US17140342
申请日：2021-01-04
Applicant: X-FAB Global Services GmbH
Inventor： Steffen Leopold
CPC classification number: B81C1/00158 , B81B3/0021 , B81B2201/0264 , B81B2203/019 , B81B2203/0127 , B81C2201/0125 , B81C2201/0132 , B81C2201/0133 , G01L9/0045
Abstract: The present invention relates to a method for manufacturing a membrane component with a membrane made of a thin film (
-
Patent Agency Ranking
公开(公告)号：US11697586B2
公开(公告)日：2023-07-11
申请号：US17027751
申请日：2020-09-22
Applicant: Teknologian tutkimuskeskus VTT Oy
Inventor： Aarne Oja , Jaakko Saarilahti
CPC classification number: B81B7/0048 , B81C1/00325 , G01L9/0072 , B81B2201/0264 , B81B2201/0271 , B81B2203/0127 , B81B2203/04 , B81C2201/0132
Abstract: The present publication discloses a micromechanical structure including at least one active element, the micromechanical structure comprising a substrate, at least one layer formed on the substrate forming the at least part of the at least one active element, mechanical contact areas through which the micromechanical structure can be connected to other structures like printed circuit boards and like. In accordance with the invention the micromechanical structure includes weakenings like trenches around the mechanical contact areas for eliminating the thermal mismatch between the active element of the micromechanical structure and the other structures.
-
公开(公告)号：US11679976B2
公开(公告)日：2023-06-20
申请号：US16776098
申请日：2020-01-29
Applicant: SEIKO EPSON CORPORATION
Inventor： Shogo Inaba
IPC: G01P15/125 , B81C1/00 , B81B3/00
CPC classification number: B81C1/00515 , G01P15/125 , B81B3/0021 , B81B2201/0235 , B81B2203/0118 , B81B2203/0353 , B81B2203/04 , B81C2201/0112 , B81C2201/0132 , B81C2201/0142
Abstract: A structure forming method according to an aspect is a structure forming method for forming a first hole and a second hole having width smaller than width of the first hole in a substrate with dry etching and forming a structure. The structure forming method includes forming an etching mask on the substrate, etching a portion of the etching mask overlapping a first hole forming region where the first hole is formed, etching a portion of the etching mask overlapping a second hole forming region where the second hole is formed, and performing the dry etching of the substrate using the etching mask as a mask.
-
公开(公告)号：US20190119099A1
公开(公告)日：2019-04-25
申请号：US16229902
申请日：2018-12-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jui Chen , I-Shi Wang , Ren-Dou Lee , Jen-Hao Liu
CPC classification number: B81B3/0005 , B81B3/001 , B81B2203/04 , B81B2207/012 , B81B2207/07 , B81C1/00984 , B81C2201/0132 , B81C2203/037 , B81C2203/0785
Abstract: The present disclosure relates to a method for manufacturing a microelectromechanical systems (MEMS) package. The method comprises providing a CMOS IC including CMOS devices arranged within a CMOS substrate. The method further comprises forming and patterning a metal layer over the CMOS substrate to form an anti-stiction layer and a fixed electrode plate and forming a rough top surface for the anti-stiction layer. The method further comprises providing a MEMS IC comprising a moveable mass arranged within a recess of a MEMS substrate and bonding the CMOS IC to the MEMS IC to enclose a cavity between the moveable mass and the fixed electrode plate and the anti-stiction layer.
-
公开(公告)号：US20190013179A1
公开(公告)日：2019-01-10
申请号：US16069796
申请日：2016-03-18
Applicant: HITACHI, LTD.
Inventor： Tetsufumi KAWAMURA , Misuzu SAGAWA , Kazuki WATANABE , Keiji WATANABE , Shuntaro MACHIDA , Nobuyuki SUGII , Daisuke RYUZAKI
IPC: H01J37/28 , H01L21/3065 , B81C1/00 , H01L21/66 , H01J37/305 , H01J37/302
CPC classification number: H01J37/28 , B81C1/00 , B81C2201/0132 , H01J37/3023 , H01J37/3056 , H01J2237/30411 , H01J2237/31745 , H01J2237/31749 , H01L21/3065 , H01L22/26
Abstract: The invention is directed to a technique for reducing the time from the start of fabrication of a prototype structure to the completion of fabrication of a real structure. A device processing method includes steps of: fabricating a first structure using an ion beam under a first condition in a first region on a substrate; measuring a size of the first structure which is fabricated; comparing the measurement result with design data; determining a second condition from the comparison result; and fabricating a second structure using the ion beam under the second condition in a second region on the substrate.
-
公开(公告)号：US20180229235A1
公开(公告)日：2018-08-16
申请号：US15434043
申请日：2017-02-15
Applicant: International Business Machines Corporation
Inventor： Joshua T. Smith , Cornelia Tsang Yang , Benjamin H. Wunsch
CPC classification number: B01L3/502707 , B01L3/502761 , B01L2200/0631 , B01L2200/0652 , B01L2200/12 , B01L2300/0816 , B01L2300/0887 , B01L2300/12 , B81B2201/058 , B81C1/00119 , B81C2201/0132 , B81C2201/0194 , B81C2203/036
Abstract: An apparatus for sorting macromolecules includes a first chip including a channel formed in a first side of the first chip and having at least one monolithic sorting structure for sorting macromolecules from the sample fluid. A first set of vias formed in the first chip has openings in a second side of the first chip, the sample fluid being provided to the sorting structure through the first set of vias. A second set of vias formed in the first chip has openings in the second side for receiving macromolecules in the sample fluid greater than or equal to a prescribed dimension sorted by the sorting structure. A third set of vias formed in the first chip has openings in the second side for receiving macromolecules in the sample fluid less than the prescribed dimension. The apparatus includes first and second seals covering the first and second sides, respectively.
-
-
-
-
-
-
-
-
-
Search Results
657
records
(took 0.02 seconds)
